[llvm] r190746 - Fixed bug when generating Load Upper Immediate microMIPS instruction.

[Zoran Jovanovic]

Author: zjovanovic
Date: Sat Sep 14 02:35:41 2013
New Revision: 190746

URL: http://llvm.org/viewvc/llvm-project?rev=190746&view=rev
Log:
Fixed bug when generating Load Upper Immediate microMIPS instruction.

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
    llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
    llvm/trunk/test/MC/Mips/micromips-alu-instructions.s

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=190746&r1=190745&r2=190746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Sat Sep 14 02:35:41 2013
@@ -363,7 +363,7 @@ class CLO_FM<bits<6> funct> : StdArch {
   let rt = rd;
 }
 
-class LUI_FM {
+class LUI_FM : StdArch {
   bits<5> rt;
   bits<16> imm16;
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=190746&r1=190745&r2=190746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Sat Sep 14 02:35:41 2013
@@ -447,7 +447,7 @@ class shift_rotate_reg<string opstr, Reg
 // Load Upper Imediate
 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
   InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
-         [], IIArith, FrmI>, IsAsCheapAsAMove {
+         [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
   let neverHasSideEffects = 1;
   let isReMaterializable = 1;
 }

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=190746&r1=190745&r2=190746&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Sat Sep 14 02:35:41 2013
@@ -49,6 +49,9 @@
 # CHECK: sltu $3, $3, $5
 0x00 0xa3 0x1b 0x90
 
+# CHECK: lui $9, 17767
+0x41 0xa9 0x45 0x67
+
 # CHECK: and $9, $6, $7
 0x00 0xe6 0x4a 0x50
 

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=190746&r1=190745&r2=190746&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Sat Sep 14 02:35:41 2013
@@ -49,6 +49,9 @@
 # CHECK: sltu $3, $3, $5
 0xa3 0x00 0x90 0x1b
 
+# CHECK: lui $9, 17767
+0xa9 0x41 0x67 0x45
+
 # CHECK: and $9, $6, $7
 0xe6 0x00 0x50 0x4a
 

Modified: llvm/trunk/test/MC/Mips/micromips-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-alu-instructions.s?rev=190746&r1=190745&r2=190746&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-alu-instructions.s Sat Sep 14 02:35:41 2013
@@ -23,6 +23,7 @@
 # CHECK-EL: slti   $3, $3, 103    # encoding: [0x63,0x90,0x67,0x00]
 # CHECK-EL: sltiu  $3, $3, 103    # encoding: [0x63,0xb0,0x67,0x00]
 # CHECK-EL: sltu   $3, $3, $5     # encoding: [0xa3,0x00,0x90,0x1b]
+# CHECK-EL: lui    $9, 17767      # encoding: [0xa9,0x41,0x67,0x45]
 # CHECK-EL: and    $9, $6, $7     # encoding: [0xe6,0x00,0x50,0x4a]
 # CHECK-EL: andi   $9, $6, 17767  # encoding: [0x26,0xd1,0x67,0x45]
 # CHECK-EL: andi   $9, $6, 17767  # encoding: [0x26,0xd1,0x67,0x45]
@@ -57,6 +58,7 @@
 # CHECK-EB: slti  $3, $3, 103     # encoding: [0x90,0x63,0x00,0x67]
 # CHECK-EB: sltiu $3, $3, 103     # encoding: [0xb0,0x63,0x00,0x67]
 # CHECK-EB: sltu  $3, $3, $5      # encoding: [0x00,0xa3,0x1b,0x90]
+# CHECK-EB: lui $9, 17767         # encoding: [0x41,0xa9,0x45,0x67]
 # CHECK-EB: and $9, $6, $7        # encoding: [0x00,0xe6,0x4a,0x50]
 # CHECK-EB:  andi  $9, $6, 17767  # encoding: [0xd1,0x26,0x45,0x67]
 # CHECK-EB:  andi  $9, $6, 17767  # encoding: [0xd1,0x26,0x45,0x67]
@@ -88,6 +90,7 @@
     slti   $3, $3, 103
     sltiu  $3, $3, 103
     sltu   $3, $3, $5
+    lui    $9, 17767
     and    $9, $6, $7
     and    $9, $6, 17767
     andi   $9, $6, 17767