[llvm] r190745 - Support for microMIPS DIV instructions.

[Zoran Jovanovic]

Author: zjovanovic
Date: Sat Sep 14 02:15:21 2013
New Revision: 190745

URL: http://llvm.org/viewvc/llvm-project?rev=190745&view=rev
Log:
Support for microMIPS DIV instructions.

Modified:
    llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
    llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
    llvm/trunk/test/MC/Mips/micromips-alu-instructions.s

Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=190745&r1=190744&r2=190745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Sat Sep 14 02:15:21 2013
@@ -69,6 +69,10 @@ let DecoderNamespace = "MicroMips", Pred
                  MULT_FM_MM<0x22c>;
   def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
                  MULT_FM_MM<0x26c>;
+  def SDIV_MM  : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
+                 MULT_FM_MM<0x2ac>;
+  def UDIV_MM  : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
+                 MULT_FM_MM<0x2ec>;
 
   /// Shift Instructions
   def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=190745&r1=190744&r2=190745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Sat Sep 14 02:15:21 2013
@@ -681,7 +681,7 @@ class MAddSubPseudo<Instruction RealInst
 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
           list<Register> DefRegs> :
   InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
-         [], itin, FrmR> {
+         [], itin, FrmR, opstr> {
   let Defs = DefRegs;
 }
 

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=190745&r1=190744&r2=190745&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Sat Sep 14 02:15:21 2013
@@ -88,6 +88,12 @@
 # CHECK: multu $9, $7
 0x00 0xe9 0x9b 0x3c
 
+# CHECK-EB: div $zero, $9, $7
+0x00 0xe9 0xab 0x3c
+
+# CHECK-EB: divu $zero, $9, $7
+0x00 0xe9 0xbb 0x3c
+
 # CHECK: sll $4, $3, 7
 0x00 0x83 0x38 0x00
 

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=190745&r1=190744&r2=190745&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Sat Sep 14 02:15:21 2013
@@ -88,6 +88,12 @@
 # CHECK: multu $9, $7
 0xe9 0x00 0x3c 0x9b
 
+# CHECK: div $zero, $9, $7
+0xe9 0x00 0x3c 0xab
+
+# CHECK: divu $zero, $9, $7
+0xe9 0x00 0x3c 0xbb
+
 # CHECK: sll $4, $3, 7
 0x83 0x00 0x00 0x38
 

Modified: llvm/trunk/test/MC/Mips/micromips-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-alu-instructions.s?rev=190745&r1=190744&r2=190745&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-alu-instructions.s Sat Sep 14 02:15:21 2013
@@ -36,6 +36,8 @@
 # CHECK-EL: mul    $9, $6, $7     # encoding: [0xe6,0x00,0x10,0x4a]
 # CHECK-EL: mult   $9, $7         # encoding: [0xe9,0x00,0x3c,0x8b]
 # CHECK-EL: multu  $9, $7         # encoding: [0xe9,0x00,0x3c,0x9b]
+# CHECK-EL: div    $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xab]
+# CHECK-EL: divu   $zero, $9, $7  # encoding: [0xe9,0x00,0x3c,0xbb]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -68,6 +70,8 @@
 # CHECK-EB:  mul $9, $6, $7       # encoding: [0x00,0xe6,0x4a,0x10]
 # CHECK-EB:  mult  $9, $7         # encoding: [0x00,0xe9,0x8b,0x3c]
 # CHECK-EB:  multu $9, $7         # encoding: [0x00,0xe9,0x9b,0x3c]
+# CHECK-EB: div  $zero, $9, $7    # encoding: [0x00,0xe9,0xab,0x3c]
+# CHECK-EB: divu $zero, $9, $7    # encoding: [0x00,0xe9,0xbb,0x3c]
     add    $9, $6, $7
     add    $9, $6, 17767
     addu   $9, $6, -15001
@@ -97,3 +101,5 @@
     mul    $9, $6, $7
     mult   $9, $7
     multu  $9, $7
+    div    $0, $9, $7
+    divu   $0, $9, $7