[llvm] r190014 - mi-sched: Force bottom up scheduling for generic targets.
Andrew Trick
atrick at apple.com
Wed Sep 4 19:03:11 PDT 2013
On Sep 4, 2013, at 5:27 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
>> Author: atrick
>> Date: Wed Sep 4 18:54:00 2013
>> New Revision: 190014
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=190014&view=rev
>> Log:
>> mi-sched: Force bottom up scheduling for generic targets.
>>
>> Fast register pressure tracking currently only takes effect during
>> bottom up scheduling. Forcing this is a bit faster and simpler for
>> targets that don't have many scheduling constraints and don't need
>> top-down scheduling.
>
> Can you please add this to TargetSubtargetInfo instead (or in addition to the command line parameters)?
Yes. I think I can do better then that. How about letting the subtarget override the generic scheduling policy for each region:
> Thanks again,
> Hal
>
>>
>> Modified:
>> llvm/trunk/lib/CodeGen/MachineScheduler.cpp
>> llvm/trunk/test/CodeGen/X86/misched-copy.ll
>> llvm/trunk/test/CodeGen/X86/misched-matmul.ll
>>
>> Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=190014&r1=190013&r2=190014&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Wed Sep 4 18:54:00
>> 2013
>> @@ -1594,6 +1594,12 @@ private:
>> SchedBoundary Top;
>> SchedBoundary Bot;
>>
>> + // Allow the driver to force top-down or bottom-up scheduling. If
>> neither is
>> + // true, the scheduler runs in both directions and converges. For
>> generic
>> + // targets, we default to bottom-up, because it's simpler and more
>> + // compile-time optimizations have been implemented in that
>> direction.
>> + bool OnlyBottomUp;
>> + bool OnlyTopDown;
>> public:
>> /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
>> enum {
>> @@ -1604,7 +1610,8 @@ public:
>>
>> ConvergingScheduler(const MachineSchedContext *C):
>> Context(C), DAG(0), SchedModel(0), TRI(0),
>> - Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
>> + Top(TopQID, "TopQ"), Bot(BotQID, "BotQ"),
>> + OnlyBottomUp(true), OnlyTopDown(false) {}
>>
>> virtual bool shouldTrackPressure(unsigned NumRegionInstrs);
>>
>> @@ -1709,6 +1716,19 @@ void ConvergingScheduler::initialize(Sch
>> }
>> assert((!ForceTopDown || !ForceBottomUp) &&
>> "-misched-topdown incompatible with -misched-bottomup");
>> +
>> + // Check -misched-topdown/bottomup can force or unforce scheduling
>> direction.
>> + // e.g. -misched-bottomup=false allows scheduling in both
>> directions.
>> + if (ForceBottomUp.getNumOccurrences() > 0) {
>> + OnlyBottomUp = ForceBottomUp;
>> + if (OnlyBottomUp)
>> + OnlyTopDown = false;
>> + }
>> + if (ForceTopDown.getNumOccurrences() > 0) {
>> + OnlyTopDown = ForceTopDown;
>> + if (OnlyTopDown)
>> + OnlyBottomUp = false;
>> + }
>> }
>>
>> void ConvergingScheduler::releaseTopNode(SUnit *SU) {
>> @@ -2674,7 +2694,7 @@ SUnit *ConvergingScheduler::pickNode(boo
>> }
>> SUnit *SU;
>> do {
>> - if (ForceTopDown) {
>> + if (OnlyTopDown) {
>> SU = Top.pickOnlyChoice();
>> if (!SU) {
>> CandPolicy NoPolicy;
>> @@ -2686,7 +2706,7 @@ SUnit *ConvergingScheduler::pickNode(boo
>> }
>> IsTopNode = true;
>> }
>> - else if (ForceBottomUp) {
>> + else if (OnlyBottomUp) {
>> SU = Bot.pickOnlyChoice();
>> if (!SU) {
>> CandPolicy NoPolicy;
>>
>> Modified: llvm/trunk/test/CodeGen/X86/misched-copy.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-copy.ll?rev=190014&r1=190013&r2=190014&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/misched-copy.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/misched-copy.ll Wed Sep 4 18:54:00
>> 2013
>> @@ -1,12 +1,4 @@
>> ; REQUIRES: asserts
>> -;
>> -; FIXME: The following line is a hack to remove any stray files
>> which might have
>> -; been left dangling around by this test. It can be removed once the
>> various
>> -; bots have cycled past this commit.
>> -;
>> -; RUN: rm -f misched-copy.s %S/misched-copy.s
>> -;
>> -;
>> ; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source
>> -enable-misched -verify-misched -debug-only=misched -o - 2>&1 >
>> /dev/null | FileCheck %s
>> ;
>> ; Test scheduling of copy instructions.
>> @@ -16,11 +8,11 @@
>> ; MUL_HiLo PhysReg use copies should be just above the mul.
>> ; MUL_HiLo PhysReg def copies should be just below the mul.
>> ;
>> -; CHECK: *** Final schedule for BB#1 ***
>> -; CHECK-NEXT: %EAX<def> = COPY
>> -; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>,
>> %EFLAGS<imp-def,dead>, %EAX<imp-use>;
>> -; CHECK-NEXT: COPY %E{{[AD]}}X;
>> -; CHECK-NEXT: COPY %E{{[AD]}}X;
>> +; CHECK: *** Final schedule for BB#1 ***
>> +; CHECK: %EAX<def> = COPY
>> +; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>,
>> %EFLAGS<imp-def,dead>, %EAX<imp-use>;
>> +; CHECK-NEXT: COPY %E{{[AD]}}X
>> +; CHECK-NEXT: COPY %E{{[AD]}}X
>> ; CHECK: DIVSSrm
>> define i64 @mulhoist(i32 %a, i32 %b) #0 {
>> entry:
>>
>> Modified: llvm/trunk/test/CodeGen/X86/misched-matmul.ll
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-matmul.ll?rev=190014&r1=190013&r2=190014&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/misched-matmul.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/misched-matmul.ll Wed Sep 4 18:54:00
>> 2013
>> @@ -3,11 +3,14 @@
>> ;
>> ; Verify that register pressure heuristics are working in
>> MachineScheduler.
>> ;
>> -; When we enable subtree scheduling heuristics on X86, we may need a
>> -; flag to disable it for this test case.
>> +; We can further reduce spills in this case with a global register
>> +; pressure heuristic, like sethi-ullman numbers or biasing toward
>> +; scheduled subtrees. However, these heuristics are marginally
>> +; beneficial on x86_64 and exacerbate register pressure in other
>> +; more complex cases.
>> ;
>> ; CHECK: @wrap_mul4
>> -; CHECK: 22 regalloc - Number of spills inserted
>> +; CHECK: 23 regalloc - Number of spills inserted
>>
>> define void @wrap_mul4(double* nocapture %Out, [4 x double]*
>> nocapture %A, [4 x double]* nocapture %B) #0 {
>> entry:
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
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>>
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
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