<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><div><div></div><br><blockquote type="cite"><div style="font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Thanks again,<br>Hal<br><br><blockquote type="cite"><br>Modified:<br> llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br> llvm/trunk/test/CodeGen/X86/misched-copy.ll<br> llvm/trunk/test/CodeGen/X86/misched-matmul.ll<br><br>Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br>URL:<br><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=190014&r1=190013&r2=190014&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=190014&r1=190013&r2=190014&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)<br>+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Wed Sep 4 18:54:00<br>2013<br>@@ -1594,6 +1594,12 @@ private:<br> SchedBoundary Top;<br> SchedBoundary Bot;<br><br>+ // Allow the driver to force top-down or bottom-up scheduling. If<br>neither is<br>+ // true, the scheduler runs in both directions and converges. For<br>generic<br>+ // targets, we default to bottom-up, because it's simpler and more<br>+ // compile-time optimizations have been implemented in that<br>direction.<br>+ bool OnlyBottomUp;<br>+ bool OnlyTopDown;<br>public:<br> /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)<br> enum {<br>@@ -1604,7 +1610,8 @@ public:<br><br> ConvergingScheduler(const MachineSchedContext *C):<br> Context(C), DAG(0), SchedModel(0), TRI(0),<br>- Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}<br>+ Top(TopQID, "TopQ"), Bot(BotQID, "BotQ"),<br>+ OnlyBottomUp(true), OnlyTopDown(false) {}<br><br> virtual bool shouldTrackPressure(unsigned NumRegionInstrs);<br><br>@@ -1709,6 +1716,19 @@ void ConvergingScheduler::initialize(Sch<br> }<br> assert((!ForceTopDown || !ForceBottomUp) &&<br> "-misched-topdown incompatible with -misched-bottomup");<br>+<br>+ // Check -misched-topdown/bottomup can force or unforce scheduling<br>direction.<br>+ // e.g. -misched-bottomup=false allows scheduling in both<br>directions.<br>+ if (ForceBottomUp.getNumOccurrences() > 0) {<br>+ OnlyBottomUp = ForceBottomUp;<br>+ if (OnlyBottomUp)<br>+ OnlyTopDown = false;<br>+ }<br>+ if (ForceTopDown.getNumOccurrences() > 0) {<br>+ OnlyTopDown = ForceTopDown;<br>+ if (OnlyTopDown)<br>+ OnlyBottomUp = false;<br>+ }<br>}<br><br>void ConvergingScheduler::releaseTopNode(SUnit *SU) {<br>@@ -2674,7 +2694,7 @@ SUnit *ConvergingScheduler::pickNode(boo<br> }<br> SUnit *SU;<br> do {<br>- if (ForceTopDown) {<br>+ if (OnlyTopDown) {<br> SU = Top.pickOnlyChoice();<br> if (!SU) {<br> CandPolicy NoPolicy;<br>@@ -2686,7 +2706,7 @@ SUnit *ConvergingScheduler::pickNode(boo<br> }<br> IsTopNode = true;<br> }<br>- else if (ForceBottomUp) {<br>+ else if (OnlyBottomUp) {<br> SU = Bot.pickOnlyChoice();<br> if (!SU) {<br> CandPolicy NoPolicy;<br><br>Modified: llvm/trunk/test/CodeGen/X86/misched-copy.ll<br>URL:<br>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-copy.ll?rev=190014&r1=190013&r2=190014&view=diff<br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/misched-copy.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/misched-copy.ll Wed Sep 4 18:54:00<br>2013<br>@@ -1,12 +1,4 @@<br>; REQUIRES: asserts<br>-;<br>-; FIXME: The following line is a hack to remove any stray files<br>which might have<br>-; been left dangling around by this test. It can be removed once the<br>various<br>-; bots have cycled past this commit.<br>-;<br>-; RUN: rm -f misched-copy.s %S/misched-copy.s<br>-;<br>-;<br>; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source<br>-enable-misched -verify-misched -debug-only=misched -o - 2>&1 ><br>/dev/null | FileCheck %s<br>;<br>; Test scheduling of copy instructions.<br>@@ -16,11 +8,11 @@<br>; MUL_HiLo PhysReg use copies should be just above the mul.<br>; MUL_HiLo PhysReg def copies should be just below the mul.<br>;<br>-; CHECK: *** Final schedule for BB#1 ***<br>-; CHECK-NEXT: %EAX<def> = COPY<br>-; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>,<br>%EFLAGS<imp-def,dead>, %EAX<imp-use>;<br>-; CHECK-NEXT: COPY %E{{[AD]}}X;<br>-; CHECK-NEXT: COPY %E{{[AD]}}X;<br>+; CHECK: *** Final schedule for BB#1 ***<br>+; CHECK: %EAX<def> = COPY<br>+; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>,<br>%EFLAGS<imp-def,dead>, %EAX<imp-use>;<br>+; CHECK-NEXT: COPY %E{{[AD]}}X<br>+; CHECK-NEXT: COPY %E{{[AD]}}X<br>; CHECK: DIVSSrm<br>define i64 @mulhoist(i32 %a, i32 %b) #0 {<br>entry:<br><br>Modified: llvm/trunk/test/CodeGen/X86/misched-matmul.ll<br>URL:<br>http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-matmul.ll?rev=190014&r1=190013&r2=190014&view=diff<br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/misched-matmul.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/misched-matmul.ll Wed Sep 4 18:54:00<br>2013<br>@@ -3,11 +3,14 @@<br>;<br>; Verify that register pressure heuristics are working in<br>MachineScheduler.<br>;<br>-; When we enable subtree scheduling heuristics on X86, we may need a<br>-; flag to disable it for this test case.<br>+; We can further reduce spills in this case with a global register<br>+; pressure heuristic, like sethi-ullman numbers or biasing toward<br>+; scheduled subtrees. However, these heuristics are marginally<br>+; beneficial on x86_64 and exacerbate register pressure in other<br>+; more complex cases.<br>;<br>; CHECK: @wrap_mul4<br>-; CHECK: 22 regalloc - Number of spills inserted<br>+; CHECK: 23 regalloc - Number of spills inserted<br><br>define void @wrap_mul4(double* nocapture %Out, [4 x double]*<br>nocapture %A, [4 x double]* nocapture %B) #0 {<br>entry:<br><br><br>_______________________________________________<br>llvm-commits mailing list<br>llvm-commits@cs.uiuc.edu<br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br><br></blockquote><br>--<span class="Apple-converted-space"> </span><br>Hal Finkel<br>Assistant Computational Scientist<br>Leadership Computing Facility<br>Argonne National Laboratory</div></blockquote></div><br></body></html>