[llvm] r189755 - FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).
NAKAMURA Takumi
geek4civic at gmail.com
Mon Sep 2 05:00:54 PDT 2013
Author: chapuni
Date: Mon Sep 2 07:00:53 2013
New Revision: 189755
URL: http://llvm.org/viewvc/llvm-project?rev=189755&view=rev
Log:
FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).
Modified:
llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll
llvm/trunk/test/CodeGen/X86/h-register-addressing-64.ll
llvm/trunk/test/CodeGen/X86/h-registers-1.ll
Modified: llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll?rev=189755&r1=189754&r2=189755&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll Mon Sep 2 07:00:53 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=-bmi | grep "movzbl %[abcd]h," | count 7
+; RUN: llc < %s -march=x86 -mattr=-bmi | FileCheck %s
; Use h-register extract and zero-extend.
@@ -9,6 +9,9 @@ define double @foo8(double* nocapture in
%t3 = load double* %t2, align 8
ret double %t3
}
+; CHECK: foo8:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
@@ -16,6 +19,9 @@ define float @foo4(float* nocapture inre
%t3 = load float* %t2, align 8
ret float %t3
}
+; CHECK: foo4:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
@@ -23,6 +29,9 @@ define i16 @foo2(i16* nocapture inreg %p
%t3 = load i16* %t2, align 8
ret i16 %t3
}
+; CHECK: foo2:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
@@ -30,6 +39,9 @@ define i8 @foo1(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: foo1:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 5
%t1 = and i32 %t0, 2040
@@ -37,6 +49,9 @@ define i8 @bar8(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar8:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 6
%t1 = and i32 %t0, 1020
@@ -44,6 +59,9 @@ define i8 @bar4(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar4:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
%t0 = lshr i32 %x, 7
%t1 = and i32 %t0, 510
@@ -51,3 +69,6 @@ define i8 @bar2(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar2:
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/h-register-addressing-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-register-addressing-64.ll?rev=189755&r1=189754&r2=189755&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-register-addressing-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-register-addressing-64.ll Mon Sep 2 07:00:53 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=-bmi | grep "movzbl %[abcd]h," | count 7
+; RUN: llc < %s -march=x86-64 -mattr=-bmi | FileCheck %s
; Use h-register extract and zero-extend.
@@ -9,6 +9,9 @@ define double @foo8(double* nocapture in
%t3 = load double* %t2, align 8
ret double %t3
}
+; CHECK: foo8:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
@@ -16,6 +19,9 @@ define float @foo4(float* nocapture inre
%t3 = load float* %t2, align 8
ret float %t3
}
+; CHECK: foo4:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
@@ -23,6 +29,9 @@ define i16 @foo2(i16* nocapture inreg %p
%t3 = load i16* %t2, align 8
ret i16 %t3
}
+; CHECK: foo2:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
@@ -30,6 +39,9 @@ define i8 @foo1(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: foo1:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 5
%t1 = and i64 %t0, 2040
@@ -37,6 +49,9 @@ define i8 @bar8(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar8:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 6
%t1 = and i64 %t0, 1020
@@ -44,6 +59,9 @@ define i8 @bar4(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar4:
+; CHECK: movzbl %{{[abcd]}}h, %e
+
define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
%t0 = lshr i64 %x, 7
%t1 = and i64 %t0, 510
@@ -51,3 +69,6 @@ define i8 @bar2(i8* nocapture inreg %p,
%t3 = load i8* %t2, align 8
ret i8 %t3
}
+; CHECK: bar2:
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: ret
Modified: llvm/trunk/test/CodeGen/X86/h-registers-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-1.ll?rev=189755&r1=189754&r2=189755&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-registers-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-registers-1.ll Mon Sep 2 07:00:53 2013
@@ -1,12 +1,21 @@
-; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux > %t
-; RUN: grep "movzbl %[abcd]h," %t | count 8
-; RUN: grep "%[abcd]h" %t | not grep "%r[[:digit:]]*d"
+; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux | FileCheck %s
; LLVM creates virtual registers for values live across blocks
; based on the type of the value. Make sure that the extracts
; here use the GR64_NOREX register class for their result,
; instead of plain GR64.
+; CHECK: foo:
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: movzbl %{{[abcd]}}h, %e
+; CHECK: ret
+
define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d,
i64 %e, i64 %f, i64 %g, i64 %h) {
%sa = lshr i64 %a, 8
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