[llvm] r189476 - [mips][msa] Added load/store intrinsics.
Daniel Sanders
daniel.sanders at imgtec.com
Wed Aug 28 05:04:29 PDT 2013
Author: dsanders
Date: Wed Aug 28 07:04:29 2013
New Revision: 189476
URL: http://llvm.org/viewvc/llvm-project?rev=189476&view=rev
Log:
[mips][msa] Added load/store intrinsics.
Added:
llvm/trunk/test/CodeGen/Mips/msa/3r_ld_st.ll
llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsMips.td
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h
Modified: llvm/trunk/include/llvm/IR/IntrinsicsMips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsMips.td?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsMips.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsMips.td Wed Aug 28 07:04:29 2013
@@ -1200,6 +1200,32 @@ def int_mips_insve_d : GCCBuiltin<"__bui
[llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty],
[IntrNoMem]>;
+def int_mips_ld_b : GCCBuiltin<"__builtin_msa_ld_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ld_h : GCCBuiltin<"__builtin_msa_ld_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ld_w : GCCBuiltin<"__builtin_msa_ld_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ld_d : GCCBuiltin<"__builtin_msa_ld_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+
+def int_mips_ldx_b : GCCBuiltin<"__builtin_msa_ldx_b">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ldx_h : GCCBuiltin<"__builtin_msa_ldx_h">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ldx_w : GCCBuiltin<"__builtin_msa_ldx_w">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+def int_mips_ldx_d : GCCBuiltin<"__builtin_msa_ldx_d">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadArgMem]>;
+
def int_mips_ldi_b : GCCBuiltin<"__builtin_msa_ldi_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_mips_ldi_h : GCCBuiltin<"__builtin_msa_ldi_h">,
@@ -1601,6 +1627,32 @@ def int_mips_srlri_w : GCCBuiltin<"__bui
def int_mips_srlri_d : GCCBuiltin<"__builtin_msa_srlri_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_mips_st_b : GCCBuiltin<"__builtin_msa_st_b">,
+ Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_st_h : GCCBuiltin<"__builtin_msa_st_h">,
+ Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_st_w : GCCBuiltin<"__builtin_msa_st_w">,
+ Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_st_d : GCCBuiltin<"__builtin_msa_st_d">,
+ Intrinsic<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+
+def int_mips_stx_b : GCCBuiltin<"__builtin_msa_stx_b">,
+ Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_stx_h : GCCBuiltin<"__builtin_msa_stx_h">,
+ Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_stx_w : GCCBuiltin<"__builtin_msa_stx_w">,
+ Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+def int_mips_stx_d : GCCBuiltin<"__builtin_msa_stx_d">,
+ Intrinsic<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty],
+ [IntrReadWriteArgMem]>;
+
def int_mips_subs_s_b : GCCBuiltin<"__builtin_msa_subs_s_b">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [Commutative]>;
def int_mips_subs_s_h : GCCBuiltin<"__builtin_msa_subs_s_h">,
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Aug 28 07:04:29 2013
@@ -69,6 +69,12 @@ bool MipsDAGToDAGISel::selectAddrRegImm(
return false;
}
+bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ llvm_unreachable("Unimplemented function.");
+ return false;
+}
+
bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
llvm_unreachable("Unimplemented function.");
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h Wed Aug 28 07:04:29 2013
@@ -57,6 +57,11 @@ private:
virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
+ // Complex Pattern.
+ /// (reg + reg).
+ virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
/// Fall back on this function if all else fails.
virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 28 07:04:29 2013
@@ -376,6 +376,9 @@ def addr :
def addrRegImm :
ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
+def addrRegReg :
+ ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
+
def addrDefault :
ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Wed Aug 28 07:04:29 2013
@@ -466,10 +466,15 @@ class LD_H_ENC : MSA_I5_FMT<0b110, 0b0
class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>;
class LD_D_ENC : MSA_I5_FMT<0b110, 0b11, 0b000111>;
-class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>;
-class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>;
-class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
-class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
+class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>;
+class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>;
+class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
+class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
+
+class LDX_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001111>;
+class LDX_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001111>;
+class LDX_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001111>;
+class LDX_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001111>;
class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
@@ -688,6 +693,11 @@ class ST_H_ENC : MSA_I5_FMT<0b111, 0b0
class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>;
class ST_D_ENC : MSA_I5_FMT<0b111, 0b11, 0b000111>;
+class STX_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001111>;
+class STX_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001111>;
+class STX_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001111>;
+class STX_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001111>;
+
class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
@@ -1705,7 +1715,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
- Operand MemOpnd = mem, ComplexPattern Addr = addr> {
+ Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm> {
dag OutOperandList = (outs RCWD:$wd);
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
@@ -1727,6 +1737,21 @@ class LDI_W_DESC : MSA_I10_DESC_BASE<"ld
class LDI_D_DESC : MSA_I10_DESC_BASE<"ldi.d", int_mips_ldi_d,
NoItinerary, MSA128D>;
+class LDX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
+ ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
+ Operand MemOpnd = mem, ComplexPattern Addr = addrRegReg> {
+ dag OutOperandList = (outs RCWD:$wd);
+ dag InOperandList = (ins MemOpnd:$addr);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
+ list<dag> Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))];
+ InstrItinClass Itinerary = itin;
+}
+
+class LDX_B_DESC : LDX_DESC_BASE<"ldx.b", load, v16i8, NoItinerary, MSA128B>;
+class LDX_H_DESC : LDX_DESC_BASE<"ldx.h", load, v8i16, NoItinerary, MSA128H>;
+class LDX_W_DESC : LDX_DESC_BASE<"ldx.w", load, v4i32, NoItinerary, MSA128W>;
+class LDX_D_DESC : LDX_DESC_BASE<"ldx.d", load, v2i64, NoItinerary, MSA128D>;
+
class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
NoItinerary, MSA128H, MSA128H>;
class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
@@ -2110,7 +2135,7 @@ class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
- Operand MemOpnd = mem, ComplexPattern Addr = addr> {
+ Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm> {
dag OutOperandList = (outs);
dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
@@ -2118,12 +2143,26 @@ class ST_DESC_BASE<string instr_asm, SDP
InstrItinClass Itinerary = itin;
}
-// Load/Store
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, NoItinerary, MSA128B>;
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, NoItinerary, MSA128H>;
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, NoItinerary, MSA128W>;
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, NoItinerary, MSA128D>;
+class STX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
+ ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
+ Operand MemOpnd = mem, ComplexPattern Addr = addrRegReg> {
+ dag OutOperandList = (outs);
+ dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr);
+ string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
+ list<dag> Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)];
+ InstrItinClass Itinerary = itin;
+}
+
+class STX_B_DESC : STX_DESC_BASE<"stx.b", store, v16i8, NoItinerary, MSA128B>;
+class STX_H_DESC : STX_DESC_BASE<"stx.h", store, v8i16, NoItinerary, MSA128H>;
+class STX_W_DESC : STX_DESC_BASE<"stx.w", store, v4i32, NoItinerary, MSA128W>;
+class STX_D_DESC : STX_DESC_BASE<"stx.d", store, v2i64, NoItinerary, MSA128D>;
+
class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
NoItinerary, MSA128B, MSA128B>;
class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
@@ -2628,6 +2667,11 @@ def LDI_B : LDI_B_ENC, LDI_B_DESC, Requi
def LDI_H : LDI_H_ENC, LDI_H_DESC, Requires<[HasMSA]>;
def LDI_W : LDI_W_ENC, LDI_W_DESC, Requires<[HasMSA]>;
+def LDX_B: LDX_B_ENC, LDX_B_DESC, Requires<[HasMSA]>;
+def LDX_H: LDX_H_ENC, LDX_H_DESC, Requires<[HasMSA]>;
+def LDX_W: LDX_W_ENC, LDX_W_DESC, Requires<[HasMSA]>;
+def LDX_D: LDX_D_ENC, LDX_D_DESC, Requires<[HasMSA]>;
+
def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC, Requires<[HasMSA]>;
def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC, Requires<[HasMSA]>;
@@ -2845,6 +2889,11 @@ def ST_H: ST_H_ENC, ST_H_DESC, Requires<
def ST_W: ST_W_ENC, ST_W_DESC, Requires<[HasMSA]>;
def ST_D: ST_D_ENC, ST_D_DESC, Requires<[HasMSA]>;
+def STX_B: STX_B_ENC, STX_B_DESC, Requires<[HasMSA]>;
+def STX_H: STX_H_ENC, STX_H_DESC, Requires<[HasMSA]>;
+def STX_W: STX_W_ENC, STX_W_DESC, Requires<[HasMSA]>;
+def STX_D: STX_D_ENC, STX_D_DESC, Requires<[HasMSA]>;
+
def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC, Requires<[HasMSA]>;
def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC, Requires<[HasMSA]>;
def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC, Requires<[HasMSA]>;
@@ -2888,19 +2937,39 @@ def XORI_B : XORI_B_ENC, XORI_B_DESC, Re
class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
Pat<pattern, result>, Requires<pred>;
-def LD_FH : MSAPat<(v8f16 (load addr:$addr)),
- (LD_H addr:$addr)>;
-def LD_FW : MSAPat<(v4f32 (load addr:$addr)),
- (LD_W addr:$addr)>;
-def LD_FD : MSAPat<(v2f64 (load addr:$addr)),
- (LD_D addr:$addr)>;
-
-def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
- (ST_H MSA128H:$ws, addr:$addr)>;
-def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
- (ST_W MSA128W:$ws, addr:$addr)>;
-def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
- (ST_D MSA128D:$ws, addr:$addr)>;
+def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
+def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
+def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
+def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
+def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
+def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
+def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
+
+def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
+def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
+def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
+
+def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
+ (ST_B MSA128B:$ws, addr:$addr)>;
+def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
+ (ST_H MSA128H:$ws, addr:$addr)>;
+def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
+ (ST_W MSA128W:$ws, addr:$addr)>;
+def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
+ (ST_D MSA128D:$ws, addr:$addr)>;
+def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
+ (ST_H MSA128H:$ws, addr:$addr)>;
+def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
+ (ST_W MSA128W:$ws, addr:$addr)>;
+def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
+ (ST_D MSA128D:$ws, addr:$addr)>;
+
+def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
+ (ST_H MSA128H:$ws, addrRegImm:$addr)>;
+def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
+ (ST_W MSA128W:$ws, addrRegImm:$addr)>;
+def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
+ (ST_D MSA128D:$ws, addrRegImm:$addr)>;
class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Wed Aug 28 07:04:29 2013
@@ -316,6 +316,20 @@ bool MipsSEDAGToDAGISel::selectAddrRegIm
return false;
}
+/// ComplexPattern used on MipsInstrInfo
+/// Used on Mips Load/Store instructions
+bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const {
+ // Operand is a result from an ADD.
+ if (Addr.getOpcode() == ISD::ADD) {
+ Base = Addr.getOperand(0);
+ Offset = Addr.getOperand(1);
+ return true;
+ }
+
+ return false;
+}
+
bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const {
Base = Addr;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h Wed Aug 28 07:04:29 2013
@@ -43,6 +43,9 @@ private:
virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
+ virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Wed Aug 28 07:04:29 2013
@@ -125,6 +125,9 @@ MipsSETargetLowering::MipsSETargetLoweri
setTargetDAGCombine(ISD::SUBE);
setTargetDAGCombine(ISD::MUL);
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
+
computeRegisterProperties();
}
@@ -174,6 +177,7 @@ SDValue MipsSETargetLowering::LowerOpera
DAG);
case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
+ case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
}
return MipsTargetLowering::LowerOperation(Op, DAG);
@@ -726,9 +730,24 @@ SDValue MipsSETargetLowering::lowerINTRI
}
}
+static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
+ SDLoc DL(Op);
+ SDValue ChainIn = Op->getOperand(0);
+ SDValue Address = Op->getOperand(2);
+ SDValue Offset = Op->getOperand(3);
+ EVT ResTy = Op->getValueType(0);
+ EVT PtrTy = Address->getValueType(0);
+
+ Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
+
+ return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
+ false, false, 16);
+}
+
SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
- switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
+ unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
+ switch (Intr) {
default:
return SDValue();
case Intrinsic::mips_extp:
@@ -771,6 +790,47 @@ SDValue MipsSETargetLowering::lowerINTRI
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
case Intrinsic::mips_dpsqx_sa_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
+ case Intrinsic::mips_ld_b:
+ case Intrinsic::mips_ld_h:
+ case Intrinsic::mips_ld_w:
+ case Intrinsic::mips_ld_d:
+ case Intrinsic::mips_ldx_b:
+ case Intrinsic::mips_ldx_h:
+ case Intrinsic::mips_ldx_w:
+ case Intrinsic::mips_ldx_d:
+ return lowerMSALoadIntr(Op, DAG, Intr);
+ }
+}
+
+static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
+ SDLoc DL(Op);
+ SDValue ChainIn = Op->getOperand(0);
+ SDValue Value = Op->getOperand(2);
+ SDValue Address = Op->getOperand(3);
+ SDValue Offset = Op->getOperand(4);
+ EVT PtrTy = Address->getValueType(0);
+
+ Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
+
+ return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
+ false, 16);
+}
+
+SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
+ SelectionDAG &DAG) const {
+ unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
+ switch (Intr) {
+ default:
+ return SDValue();
+ case Intrinsic::mips_st_b:
+ case Intrinsic::mips_st_h:
+ case Intrinsic::mips_st_w:
+ case Intrinsic::mips_st_d:
+ case Intrinsic::mips_stx_b:
+ case Intrinsic::mips_stx_h:
+ case Intrinsic::mips_stx_w:
+ case Intrinsic::mips_stx_d:
+ return lowerMSAStoreIntr(Op, DAG, Intr);
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h?rev=189476&r1=189475&r2=189476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h Wed Aug 28 07:04:29 2013
@@ -63,6 +63,7 @@ namespace llvm {
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
MachineBasicBlock *BB) const;
Added: llvm/trunk/test/CodeGen/Mips/msa/3r_ld_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_ld_st.ll?rev=189476&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_ld_st.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_ld_st.ll Wed Aug 28 07:04:29 2013
@@ -0,0 +1,149 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format and
+; are loads or stores.
+
+; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+
+ at llvm_mips_ldx_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_ldx_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_ldx_b_test(i32 %a1) nounwind {
+entry:
+ %0 = bitcast <16 x i8>* @llvm_mips_ldx_b_ARG to i8*
+ %1 = tail call <16 x i8> @llvm.mips.ldx.b(i8* %0, i32 %a1)
+ store <16 x i8> %1, <16 x i8>* @llvm_mips_ldx_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.ldx.b(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ldx_b_test:
+; CHECK: ldx.b [[R1:\$w[0-9]+]], $4(
+; CHECK: st.b
+; CHECK: .size llvm_mips_ldx_b_test
+;
+ at llvm_mips_ldx_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_ldx_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_ldx_h_test(i32 %a1) nounwind {
+entry:
+ %0 = bitcast <8 x i16>* @llvm_mips_ldx_h_ARG to i8*
+ %1 = tail call <8 x i16> @llvm.mips.ldx.h(i8* %0, i32 %a1)
+ store <8 x i16> %1, <8 x i16>* @llvm_mips_ldx_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.ldx.h(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ldx_h_test:
+; CHECK: ldx.h [[R1:\$w[0-9]+]], $4(
+; CHECK: st.h
+; CHECK: .size llvm_mips_ldx_h_test
+;
+ at llvm_mips_ldx_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_ldx_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_ldx_w_test(i32 %a1) nounwind {
+entry:
+ %0 = bitcast <4 x i32>* @llvm_mips_ldx_w_ARG to i8*
+ %1 = tail call <4 x i32> @llvm.mips.ldx.w(i8* %0, i32 %a1)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_ldx_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.ldx.w(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ldx_w_test:
+; CHECK: ldx.w [[R1:\$w[0-9]+]], $4(
+; CHECK: st.w
+; CHECK: .size llvm_mips_ldx_w_test
+;
+ at llvm_mips_ldx_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_ldx_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_ldx_d_test(i32 %a1) nounwind {
+entry:
+ %0 = bitcast <2 x i64>* @llvm_mips_ldx_d_ARG to i8*
+ %1 = tail call <2 x i64> @llvm.mips.ldx.d(i8* %0, i32 %a1)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_ldx_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.ldx.d(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ldx_d_test:
+; CHECK: ldx.d [[R1:\$w[0-9]+]], $4(
+; CHECK: st.d
+; CHECK: .size llvm_mips_ldx_d_test
+;
+ at llvm_mips_stx_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_stx_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_stx_b_test(i32 %a1) nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_stx_b_ARG
+ %1 = bitcast <16 x i8>* @llvm_mips_stx_b_RES to i8*
+ tail call void @llvm.mips.stx.b(<16 x i8> %0, i8* %1, i32 %a1)
+ ret void
+}
+
+declare void @llvm.mips.stx.b(<16 x i8>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_stx_b_test:
+; CHECK: ld.b
+; CHECK: stx.b [[R1:\$w[0-9]+]], $4(
+; CHECK: .size llvm_mips_stx_b_test
+;
+ at llvm_mips_stx_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_stx_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_stx_h_test(i32 %a1) nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_stx_h_ARG
+ %1 = bitcast <8 x i16>* @llvm_mips_stx_h_RES to i8*
+ tail call void @llvm.mips.stx.h(<8 x i16> %0, i8* %1, i32 %a1)
+ ret void
+}
+
+declare void @llvm.mips.stx.h(<8 x i16>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_stx_h_test:
+; CHECK: ld.h
+; CHECK: stx.h [[R1:\$w[0-9]+]], $4(
+; CHECK: .size llvm_mips_stx_h_test
+;
+ at llvm_mips_stx_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_stx_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_stx_w_test(i32 %a1) nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_stx_w_ARG
+ %1 = bitcast <4 x i32>* @llvm_mips_stx_w_RES to i8*
+ tail call void @llvm.mips.stx.w(<4 x i32> %0, i8* %1, i32 %a1)
+ ret void
+}
+
+declare void @llvm.mips.stx.w(<4 x i32>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_stx_w_test:
+; CHECK: ld.w
+; CHECK: stx.w [[R1:\$w[0-9]+]], $4(
+; CHECK: .size llvm_mips_stx_w_test
+;
+ at llvm_mips_stx_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_stx_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_stx_d_test(i32 %a1) nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_stx_d_ARG
+ %1 = bitcast <2 x i64>* @llvm_mips_stx_d_RES to i8*
+ tail call void @llvm.mips.stx.d(<2 x i64> %0, i8* %1, i32 %a1)
+ ret void
+}
+
+declare void @llvm.mips.stx.d(<2 x i64>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_stx_d_test:
+; CHECK: ld.d
+; CHECK: stx.d [[R1:\$w[0-9]+]], $4(
+; CHECK: .size llvm_mips_stx_d_test
+;
Added: llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll?rev=189476&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll Wed Aug 28 07:04:29 2013
@@ -0,0 +1,149 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format and
+; are loads or stores.
+
+; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+
+ at llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_ld_b_test() nounwind {
+entry:
+ %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
+ %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
+ store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
+ ret void
+}
+
+declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ld_b_test:
+; CHECK: ld.b [[R1:\$w[0-9]+]], 16(
+; CHECK: st.b
+; CHECK: .size llvm_mips_ld_b_test
+;
+ at llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_ld_h_test() nounwind {
+entry:
+ %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
+ %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
+ store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
+ ret void
+}
+
+declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ld_h_test:
+; CHECK: ld.h [[R1:\$w[0-9]+]], 16(
+; CHECK: st.h
+; CHECK: .size llvm_mips_ld_h_test
+;
+ at llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_ld_w_test() nounwind {
+entry:
+ %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
+ %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16)
+ store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
+ ret void
+}
+
+declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ld_w_test:
+; CHECK: ld.w [[R1:\$w[0-9]+]], 16(
+; CHECK: st.w
+; CHECK: .size llvm_mips_ld_w_test
+;
+ at llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_ld_d_test() nounwind {
+entry:
+ %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
+ %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16)
+ store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
+ ret void
+}
+
+declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
+
+; CHECK: llvm_mips_ld_d_test:
+; CHECK: ld.d [[R1:\$w[0-9]+]], 16(
+; CHECK: st.d
+; CHECK: .size llvm_mips_ld_d_test
+;
+ at llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
+ at llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
+
+define void @llvm_mips_st_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_st_b_ARG
+ %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
+ tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16)
+ ret void
+}
+
+declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_st_b_test:
+; CHECK: ld.b
+; CHECK: st.b [[R1:\$w[0-9]+]], 16(
+; CHECK: .size llvm_mips_st_b_test
+;
+ at llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
+ at llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
+
+define void @llvm_mips_st_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_st_h_ARG
+ %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
+ tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 16)
+ ret void
+}
+
+declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_st_h_test:
+; CHECK: ld.h
+; CHECK: st.h [[R1:\$w[0-9]+]], 16(
+; CHECK: .size llvm_mips_st_h_test
+;
+ at llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
+ at llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
+
+define void @llvm_mips_st_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_st_w_ARG
+ %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
+ tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 16)
+ ret void
+}
+
+declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_st_w_test:
+; CHECK: ld.w
+; CHECK: st.w [[R1:\$w[0-9]+]], 16(
+; CHECK: .size llvm_mips_st_w_test
+;
+ at llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
+ at llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_st_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_st_d_ARG
+ %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
+ tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 16)
+ ret void
+}
+
+declare void @llvm.mips.st.d(<2 x i64>, i8*, i32) nounwind
+
+; CHECK: llvm_mips_st_d_test:
+; CHECK: ld.d
+; CHECK: st.d [[R1:\$w[0-9]+]], 16(
+; CHECK: .size llvm_mips_st_d_test
+;
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