[llvm] r186686 - [SystemZ] Add ARK, AGRK, SRK and SGRK
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Fri Jul 19 09:26:40 PDT 2013
Author: rsandifo
Date: Fri Jul 19 11:26:39 2013
New Revision: 186686
URL: http://llvm.org/viewvc/llvm-project?rev=186686&view=rev
Log:
[SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.
Added:
llvm/trunk/test/CodeGen/SystemZ/int-add-13.ll
llvm/trunk/test/CodeGen/SystemZ/int-sub-08.ll
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
llvm/trunk/test/CodeGen/SystemZ/int-add-02.ll
llvm/trunk/test/CodeGen/SystemZ/int-add-05.ll
llvm/trunk/test/CodeGen/SystemZ/int-sub-01.ll
llvm/trunk/test/CodeGen/SystemZ/int-sub-04.ll
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Fri Jul 19 11:26:39 2013
@@ -535,8 +535,8 @@ def : Pat<(or (zext32 GR32:$src), imm64h
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
- def AR : BinaryRR <"a", 0x1A, add, GR32, GR32>;
- def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>;
+ defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
+ defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
}
def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
@@ -599,9 +599,9 @@ let Defs = [CC], Uses = [CC] in {
// add-immediate instruction instead.
let Defs = [CC] in {
// Subtraction of a register.
- def SR : BinaryRR <"s", 0x1B, sub, GR32, GR32>;
+ defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
- def SGR : BinaryRRE<"sg", 0xB909, sub, GR64, GR64>;
+ defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
// Subtraction of memory.
defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-03.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,6 @@
; Test 32-bit atomic additions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-add-04.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic additions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check addition of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-03.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,6 @@
; Test 32-bit atomic subtractions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-sub-04.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic subtractions.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check subtraction of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/int-add-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-add-02.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-add-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-add-02.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,7 @@
; Test 32-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-add-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-add-05.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-add-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-add-05.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,7 @@
; Test 64-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
Added: llvm/trunk/test/CodeGen/SystemZ/int-add-13.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-add-13.ll?rev=186686&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-add-13.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/int-add-13.ll Fri Jul 19 11:26:39 2013
@@ -0,0 +1,39 @@
+; Test the three-operand forms of addition.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check ARK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ark %r2, %r3, %r4
+; CHECK: br %r14
+ %add = add i32 %b, %c
+ ret i32 %add
+}
+
+; Check that we can still use AR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: ar %r2, %r3
+; CHECK: br %r14
+ %add = add i32 %a, %b
+ ret i32 %add
+}
+
+; Check AGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: agrk %r2, %r3, %r4
+; CHECK: br %r14
+ %add = add i64 %b, %c
+ ret i64 %add
+}
+
+; Check that we can still use AGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: agr %r2, %r3
+; CHECK: br %r14
+ %add = add i64 %a, %b
+ ret i64 %add
+}
Modified: llvm/trunk/test/CodeGen/SystemZ/int-sub-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-sub-01.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-sub-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-sub-01.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,7 @@
; Test 32-bit subtraction.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/int-sub-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-sub-04.ll?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-sub-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/int-sub-04.ll Fri Jul 19 11:26:39 2013
@@ -1,6 +1,7 @@
; Test 64-bit subtraction in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
Added: llvm/trunk/test/CodeGen/SystemZ/int-sub-08.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/int-sub-08.ll?rev=186686&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/int-sub-08.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/int-sub-08.ll Fri Jul 19 11:26:39 2013
@@ -0,0 +1,39 @@
+; Test the three-operand forms of subtraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check SRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: srk %r2, %r3, %r4
+; CHECK: br %r14
+ %sub = sub i32 %b, %c
+ ret i32 %sub
+}
+
+; Check that we can still use SR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: sr %r2, %r3
+; CHECK: br %r14
+ %sub = sub i32 %a, %b
+ ret i32 %sub
+}
+
+; Check SGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: sgrk %r2, %r3, %r4
+; CHECK: br %r14
+ %sub = sub i64 %b, %c
+ ret i64 %sub
+}
+
+; Check that we can still use SGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: sgr %r2, %r3
+; CHECK: br %r14
+ %sub = sub i64 %a, %b
+ ret i64 %sub
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Fri Jul 19 11:26:39 2013
@@ -175,6 +175,12 @@
# CHECK: agr %r7, %r8
0xb9 0x08 0x00 0x78
+# CHECK: agrk %r0, %r0, %r0
+0xb9 0xe8 0x00 0x00
+
+# CHECK: agrk %r2, %r3, %r4
+0xb9 0xe8 0x40 0x23
+
# CHECK: agsi -524288, 0
0xeb 0x00 0x00 0x00 0x80 0x7a
@@ -574,6 +580,12 @@
# CHECK: ar %r7, %r8
0x1a 0x78
+# CHECK: ark %r0, %r0, %r0
+0xb9 0xf8 0x00 0x00
+
+# CHECK: ark %r2, %r3, %r4
+0xb9 0xf8 0x40 0x23
+
# CHECK: asi -524288, 0
0xeb 0x00 0x00 0x00 0x80 0x6a
@@ -4936,6 +4948,12 @@
# CHECK: sgr %r7, %r8
0xb9 0x09 0x00 0x78
+# CHECK: sgrk %r0, %r0, %r0
+0xb9 0xe9 0x00 0x00
+
+# CHECK: sgrk %r2, %r3, %r4
+0xb9 0xe9 0x40 0x23
+
# CHECK: sg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x09
@@ -5644,6 +5662,12 @@
# CHECK: sr %r7, %r8
0x1b 0x78
+# CHECK: srk %r0, %r0, %r0
+0xb9 0xf9 0x00 0x00
+
+# CHECK: srk %r2, %r3, %r4
+0xb9 0xf9 0x40 0x23
+
# CHECK: stc %r0, 0
0x42 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Fri Jul 19 11:26:39 2013
@@ -69,6 +69,11 @@
aghi %r0, 32768
aghi %r0, foo
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: agrk %r2,%r3,%r4
+
+ agrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: agsi -524289, 0
#CHECK: error: invalid operand
@@ -177,6 +182,11 @@
aly %r0, -524289
aly %r0, 524288
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ark %r2,%r3,%r4
+
+ ark %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: asi -524289, 0
#CHECK: error: invalid operand
@@ -2264,6 +2274,11 @@
sgf %r0, -524289
sgf %r0, 524288
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: sgrk %r2,%r3,%r4
+
+ sgrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: sh %r0, -1
#CHECK: error: invalid operand
@@ -2434,6 +2449,11 @@
srak %r2,%r3,4(%r5)
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: srk %r2,%r3,%r4
+
+ srk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: srl %r0,-1
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=186686&r1=186685&r2=186686&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Fri Jul 19 11:26:39 2013
@@ -1,6 +1,30 @@
# For z196 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
+#CHECK: agrk %r0, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0x00]
+#CHECK: agrk %r0, %r0, %r15 # encoding: [0xb9,0xe8,0xf0,0x00]
+#CHECK: agrk %r0, %r15, %r0 # encoding: [0xb9,0xe8,0x00,0x0f]
+#CHECK: agrk %r15, %r0, %r0 # encoding: [0xb9,0xe8,0x00,0xf0]
+#CHECK: agrk %r7, %r8, %r9 # encoding: [0xb9,0xe8,0x90,0x78]
+
+ agrk %r0,%r0,%r0
+ agrk %r0,%r0,%r15
+ agrk %r0,%r15,%r0
+ agrk %r15,%r0,%r0
+ agrk %r7,%r8,%r9
+
+#CHECK: ark %r0, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0x00]
+#CHECK: ark %r0, %r0, %r15 # encoding: [0xb9,0xf8,0xf0,0x00]
+#CHECK: ark %r0, %r15, %r0 # encoding: [0xb9,0xf8,0x00,0x0f]
+#CHECK: ark %r15, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0xf0]
+#CHECK: ark %r7, %r8, %r9 # encoding: [0xb9,0xf8,0x90,0x78]
+
+ ark %r0,%r0,%r0
+ ark %r0,%r0,%r15
+ ark %r0,%r15,%r0
+ ark %r15,%r0,%r0
+ ark %r7,%r8,%r9
+
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
@@ -49,6 +73,18 @@
ork %r15,%r0,%r0
ork %r7,%r8,%r9
+#CHECK: sgrk %r0, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0x00]
+#CHECK: sgrk %r0, %r0, %r15 # encoding: [0xb9,0xe9,0xf0,0x00]
+#CHECK: sgrk %r0, %r15, %r0 # encoding: [0xb9,0xe9,0x00,0x0f]
+#CHECK: sgrk %r15, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0xf0]
+#CHECK: sgrk %r7, %r8, %r9 # encoding: [0xb9,0xe9,0x90,0x78]
+
+ sgrk %r0,%r0,%r0
+ sgrk %r0,%r0,%r15
+ sgrk %r0,%r15,%r0
+ sgrk %r15,%r0,%r0
+ sgrk %r7,%r8,%r9
+
#CHECK: sllk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
@@ -101,6 +137,18 @@
srak %r0,%r0,524287(%r1)
srak %r0,%r0,524287(%r15)
+#CHECK: srk %r0, %r0, %r0 # encoding: [0xb9,0xf9,0x00,0x00]
+#CHECK: srk %r0, %r0, %r15 # encoding: [0xb9,0xf9,0xf0,0x00]
+#CHECK: srk %r0, %r15, %r0 # encoding: [0xb9,0xf9,0x00,0x0f]
+#CHECK: srk %r15, %r0, %r0 # encoding: [0xb9,0xf9,0x00,0xf0]
+#CHECK: srk %r7, %r8, %r9 # encoding: [0xb9,0xf9,0x90,0x78]
+
+ srk %r0,%r0,%r0
+ srk %r0,%r0,%r15
+ srk %r0,%r15,%r0
+ srk %r15,%r0,%r0
+ srk %r7,%r8,%r9
+
#CHECK: srlk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xde]
#CHECK: srlk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xde]
#CHECK: srlk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xde]
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