[llvm] r186685 - [SystemZ] Add NGRK, OGRK and XGRK
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Fri Jul 19 09:24:22 PDT 2013
Author: rsandifo
Date: Fri Jul 19 11:24:22 2013
New Revision: 186685
URL: http://llvm.org/viewvc/llvm-project?rev=186685&view=rev
Log:
[SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/and-03.ll
llvm/trunk/test/CodeGen/SystemZ/and-07.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll
llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
llvm/trunk/test/CodeGen/SystemZ/or-03.ll
llvm/trunk/test/CodeGen/SystemZ/or-07.ll
llvm/trunk/test/CodeGen/SystemZ/xor-03.ll
llvm/trunk/test/CodeGen/SystemZ/xor-07.ll
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Fri Jul 19 11:24:22 2013
@@ -747,6 +747,18 @@ multiclass BinaryRRAndK<string mnemonic,
}
}
+multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
+ SDPatternOperator operator, RegisterOperand cls1,
+ RegisterOperand cls2> {
+ let NumOpsKey = mnemonic in {
+ let NumOpsValue = "3" in
+ def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
+ Requires<[FeatureDistinctOps]>;
+ let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
+ def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
+ }
+}
+
class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
RegisterOperand cls, Immediate imm>
: InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Fri Jul 19 11:24:22 2013
@@ -649,7 +649,7 @@ let Defs = [CC] in {
// ANDs of a register.
let isCommutable = 1 in {
defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
- def NGR : BinaryRRE<"ng", 0xB980, and, GR64, GR64>;
+ defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
}
// ANDs of a 16-bit immediate, leaving other bits unaffected.
@@ -686,7 +686,7 @@ let Defs = [CC] in {
// ORs of a register.
let isCommutable = 1 in {
defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
- def OGR : BinaryRRE<"og", 0xB981, or, GR64, GR64>;
+ defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
}
// ORs of a 16-bit immediate, leaving other bits unaffected.
@@ -723,7 +723,7 @@ let Defs = [CC] in {
// XORs of a register.
let isCommutable = 1 in {
defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
- def XGR : BinaryRRE<"xg", 0xB982, xor, GR64, GR64>;
+ defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
}
// XORs of a 32-bit immediate, leaving other bits unaffected.
Modified: llvm/trunk/test/CodeGen/SystemZ/and-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-03.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-03.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,7 @@
; Test 64-bit ANDs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/and-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/and-07.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/and-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/and-07.ll Fri Jul 19 11:24:22 2013
@@ -19,3 +19,21 @@ define i32 @f2(i32 %a, i32 %b) {
%and = and i32 %a, %b
ret i32 %and
}
+
+; Check NGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: ngrk %r2, %r3, %r4
+; CHECK: br %r14
+ %and = and i64 %b, %c
+ ret i64 %and
+}
+
+; Check that we can still use NGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: ngr %r2, %r3
+; CHECK: br %r14
+ %and = and i64 %a, %b
+ ret i64 %and
+}
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-and-04.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic ANDs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check ANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-nand-04.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic NANDs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check NANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-or-04.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic ORs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check ORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/atomicrmw-xor-04.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,6 @@
; Test 64-bit atomic XORs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check XORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
Modified: llvm/trunk/test/CodeGen/SystemZ/or-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/or-03.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/or-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/or-03.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,7 @@
; Test 64-bit ORs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/or-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/or-07.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/or-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/or-07.ll Fri Jul 19 11:24:22 2013
@@ -19,3 +19,21 @@ define i32 @f2(i32 %a, i32 %b) {
%or = or i32 %a, %b
ret i32 %or
}
+
+; Check OGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: ogrk %r2, %r3, %r4
+; CHECK: br %r14
+ %or = or i64 %b, %c
+ ret i64 %or
+}
+
+; Check that we can still use OGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: ogr %r2, %r3
+; CHECK: br %r14
+ %or = or i64 %a, %b
+ ret i64 %or
+}
Modified: llvm/trunk/test/CodeGen/SystemZ/xor-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/xor-03.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/xor-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/xor-03.ll Fri Jul 19 11:24:22 2013
@@ -1,6 +1,7 @@
; Test 64-bit XORs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i64 @foo()
Modified: llvm/trunk/test/CodeGen/SystemZ/xor-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/xor-07.ll?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/xor-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/xor-07.ll Fri Jul 19 11:24:22 2013
@@ -19,3 +19,21 @@ define i32 @f2(i32 %a, i32 %b) {
%xor = xor i32 %a, %b
ret i32 %xor
}
+
+; Check XGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: xgrk %r2, %r3, %r4
+; CHECK: br %r14
+ %xor = xor i64 %b, %c
+ ret i64 %xor
+}
+
+; Check that we can still use XGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: xgr %r2, %r3
+; CHECK: br %r14
+ %xor = xor i64 %a, %b
+ ret i64 %xor
+}
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Fri Jul 19 11:24:22 2013
@@ -4207,6 +4207,12 @@
# CHECK: ng %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x80
+# CHECK: ngrk %r0, %r0, %r0
+0xb9 0xe4 0x00 0x00
+
+# CHECK: ngrk %r2, %r3, %r4
+0xb9 0xe4 0x40 0x23
+
# CHECK: ng %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x80
@@ -4432,6 +4438,12 @@
# CHECK: ogr %r7, %r8
0xb9 0x81 0x00 0x78
+# CHECK: ogrk %r0, %r0, %r0
+0xb9 0xe6 0x00 0x00
+
+# CHECK: ogrk %r2, %r3, %r4
+0xb9 0xe6 0x40 0x23
+
# CHECK: og %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x81
@@ -6091,6 +6103,12 @@
# CHECK: xgr %r7, %r8
0xb9 0x82 0x00 0x78
+# CHECK: xgrk %r0, %r0, %r0
+0xb9 0xe7 0x00 0x00
+
+# CHECK: xgrk %r2, %r3, %r4
+0xb9 0xe7 0x40 0x23
+
# CHECK: xg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x82
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Fri Jul 19 11:24:22 2013
@@ -1900,6 +1900,11 @@
ng %r0, -524289
ng %r0, 524288
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ngrk %r2,%r3,%r4
+
+ ngrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: ni -1, 0
#CHECK: error: invalid operand
@@ -2011,6 +2016,11 @@
og %r0, -524289
og %r0, 524288
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ogrk %r2,%r3,%r4
+
+ ogrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: oi -1, 0
#CHECK: error: invalid operand
@@ -2646,6 +2656,11 @@
xg %r0, -524289
xg %r0, 524288
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: xgrk %r2,%r3,%r4
+
+ xgrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: xi -1, 0
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=186685&r1=186684&r2=186685&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Fri Jul 19 11:24:22 2013
@@ -1,6 +1,18 @@
# For z196 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
+#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
+#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
+#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
+#CHECK: ngrk %r15, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0xf0]
+#CHECK: ngrk %r7, %r8, %r9 # encoding: [0xb9,0xe4,0x90,0x78]
+
+ ngrk %r0,%r0,%r0
+ ngrk %r0,%r0,%r15
+ ngrk %r0,%r15,%r0
+ ngrk %r15,%r0,%r0
+ ngrk %r7,%r8,%r9
+
#CHECK: nrk %r0, %r0, %r0 # encoding: [0xb9,0xf4,0x00,0x00]
#CHECK: nrk %r0, %r0, %r15 # encoding: [0xb9,0xf4,0xf0,0x00]
#CHECK: nrk %r0, %r15, %r0 # encoding: [0xb9,0xf4,0x00,0x0f]
@@ -13,6 +25,18 @@
nrk %r15,%r0,%r0
nrk %r7,%r8,%r9
+#CHECK: ogrk %r0, %r0, %r0 # encoding: [0xb9,0xe6,0x00,0x00]
+#CHECK: ogrk %r0, %r0, %r15 # encoding: [0xb9,0xe6,0xf0,0x00]
+#CHECK: ogrk %r0, %r15, %r0 # encoding: [0xb9,0xe6,0x00,0x0f]
+#CHECK: ogrk %r15, %r0, %r0 # encoding: [0xb9,0xe6,0x00,0xf0]
+#CHECK: ogrk %r7, %r8, %r9 # encoding: [0xb9,0xe6,0x90,0x78]
+
+ ogrk %r0,%r0,%r0
+ ogrk %r0,%r0,%r15
+ ogrk %r0,%r15,%r0
+ ogrk %r15,%r0,%r0
+ ogrk %r7,%r8,%r9
+
#CHECK: ork %r0, %r0, %r0 # encoding: [0xb9,0xf6,0x00,0x00]
#CHECK: ork %r0, %r0, %r15 # encoding: [0xb9,0xf6,0xf0,0x00]
#CHECK: ork %r0, %r15, %r0 # encoding: [0xb9,0xf6,0x00,0x0f]
@@ -103,6 +127,18 @@
srlk %r0,%r0,524287(%r1)
srlk %r0,%r0,524287(%r15)
+#CHECK: xgrk %r0, %r0, %r0 # encoding: [0xb9,0xe7,0x00,0x00]
+#CHECK: xgrk %r0, %r0, %r15 # encoding: [0xb9,0xe7,0xf0,0x00]
+#CHECK: xgrk %r0, %r15, %r0 # encoding: [0xb9,0xe7,0x00,0x0f]
+#CHECK: xgrk %r15, %r0, %r0 # encoding: [0xb9,0xe7,0x00,0xf0]
+#CHECK: xgrk %r7, %r8, %r9 # encoding: [0xb9,0xe7,0x90,0x78]
+
+ xgrk %r0,%r0,%r0
+ xgrk %r0,%r0,%r15
+ xgrk %r0,%r15,%r0
+ xgrk %r15,%r0,%r0
+ xgrk %r7,%r8,%r9
+
#CHECK: xrk %r0, %r0, %r0 # encoding: [0xb9,0xf7,0x00,0x00]
#CHECK: xrk %r0, %r0, %r15 # encoding: [0xb9,0xf7,0xf0,0x00]
#CHECK: xrk %r0, %r15, %r0 # encoding: [0xb9,0xf7,0x00,0x0f]
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