[llvm] r183608 - ARM: fix VCVT decoding

[Amaury de la Vieuville]

Author: amaury.dlv
Date: Sat Jun  8 08:29:11 2013
New Revision: 183608

URL: http://llvm.org/viewvc/llvm-project?rev=183608&view=rev
Log:
ARM: fix VCVT decoding

UNPRED was reported instead of UNDEF

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=183608&r1=183607&r2=183608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Sat Jun  8 08:29:11 2013
@@ -4441,7 +4441,7 @@ static DecodeStatus DecodeVCVTD(MCInst &
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
 
-  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+  if (!(imm & 0x20)) return MCDisassembler::Fail;
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;
@@ -4469,7 +4469,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
 
-  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+  if (!(imm & 0x20)) return MCDisassembler::Fail;
 
   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
     return MCDisassembler::Fail;

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt?rev=183608&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt Sat Jun  8 08:29:11 2013
@@ -0,0 +1,8 @@
+# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD)
+# imm6=0b0xxxxx -> UNDEFINED
+
+# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
+
+# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding