[llvm] r183458 - R600: Rewrite an awkward loop in R600MachineScheduler

[Vincent Lejeune]

Author: vljn
Date: Thu Jun  6 18:08:32 2013
New Revision: 183458

URL: http://llvm.org/viewvc/llvm-project?rev=183458&view=rev
Log:
R600: Rewrite an awkward loop in R600MachineScheduler

Modified:
    llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp

Modified: llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp?rev=183458&r1=183457&r2=183458&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600OptimizeVectorRegisters.cpp Thu Jun  6 18:08:32 2013
@@ -159,6 +159,19 @@ bool R600VectorRegMerger::tryMergeVector
   return true;
 }
 
+static
+unsigned getReassignedChan(
+    const std::vector<std::pair<unsigned, unsigned> > &RemapChan,
+    unsigned Chan) {
+  for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
+    if (RemapChan[j].first == Chan) {
+      return RemapChan[j].second;
+      break;
+    }
+  }
+  llvm_unreachable("Chan wasn't reassigned");
+}
+
 MachineInstr *R600VectorRegMerger::RebuildVector(
     RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
     const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
@@ -179,13 +192,8 @@ MachineInstr *R600VectorRegMerger::Rebui
     unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
     unsigned SubReg = (*It).first;
     unsigned Swizzle = (*It).second;
-    unsigned Chan = 0xDEADBEEF;
-    for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
-      if (RemapChan[j].first == Swizzle) {
-        Chan = RemapChan[j].second;
-        break;
-      }
-    }
+    unsigned Chan = getReassignedChan(RemapChan, Swizzle);
+
     MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
         DstReg)
         .addReg(SrcVec)