[llvm] r183336 - R600: Schedule copy from phys register at beginning of block
Vincent Lejeune
vljn at ovi.com
Wed Jun 5 13:27:35 PDT 2013
Author: vljn
Date: Wed Jun 5 15:27:35 2013
New Revision: 183336
URL: http://llvm.org/viewvc/llvm-project?rev=183336&view=rev
Log:
R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg
Modified:
llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp
llvm/trunk/lib/Target/R600/R600MachineScheduler.h
llvm/trunk/test/CodeGen/R600/fabs.ll
llvm/trunk/test/CodeGen/R600/fadd.ll
llvm/trunk/test/CodeGen/R600/floor.ll
llvm/trunk/test/CodeGen/R600/fmad.ll
llvm/trunk/test/CodeGen/R600/fmax.ll
llvm/trunk/test/CodeGen/R600/fmin.ll
llvm/trunk/test/CodeGen/R600/fmul.ll
llvm/trunk/test/CodeGen/R600/fsub.ll
llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll
llvm/trunk/test/CodeGen/R600/llvm.pow.ll
Modified: llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600MachineScheduler.cpp Wed Jun 5 15:27:35 2013
@@ -71,6 +71,10 @@ SUnit* R600SchedStrategy::pickNode(bool
(!AllowSwitchFromAlu && CurInstKind == IDAlu))) {
// try to pick ALU
SU = pickAlu();
+ if (!SU && !PhysicalRegCopy.empty()) {
+ SU = PhysicalRegCopy.front();
+ PhysicalRegCopy.erase(PhysicalRegCopy.begin());
+ }
if (SU) {
if (CurEmitted >= InstKindLimit[IDAlu])
CurEmitted = 0;
@@ -118,7 +122,22 @@ SUnit* R600SchedStrategy::pickNode(bool
return SU;
}
+bool IsUnScheduled(const SUnit *SU) {
+ return SU->isScheduled;
+}
+
+static
+void Filter(std::vector<SUnit *> &List) {
+ List.erase(std::remove_if(List.begin(), List.end(), IsUnScheduled), List.end());
+}
+
void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
+ if (IsTopNode) {
+ for (unsigned i = 0; i < AluLast; i++) {
+ Filter(Available[i]);
+ Filter(Pending[i]);
+ }
+ }
if (NextInstKind != CurInstKind) {
DEBUG(dbgs() << "Instruction Type Switch\n");
@@ -157,13 +176,24 @@ void R600SchedStrategy::schedNode(SUnit
}
}
+static bool
+isPhysicalRegCopy(MachineInstr *MI) {
+ if (MI->getOpcode() != AMDGPU::COPY)
+ return false;
+
+ return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg());
+}
+
void R600SchedStrategy::releaseTopNode(SUnit *SU) {
DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG););
-
}
void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG););
+ if (isPhysicalRegCopy(SU->getInstr())) {
+ PhysicalRegCopy.push_back(SU);
+ return;
+ }
int IK = getInstKind(SU);
Modified: llvm/trunk/lib/Target/R600/R600MachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600MachineScheduler.h?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600MachineScheduler.h (original)
+++ llvm/trunk/lib/Target/R600/R600MachineScheduler.h Wed Jun 5 15:27:35 2013
@@ -54,6 +54,7 @@ class R600SchedStrategy : public Machine
std::vector<SUnit *> AvailableAlus[AluLast];
std::vector<SUnit *> UnscheduledARDefs;
std::vector<SUnit *> UnscheduledARUses;
+ std::vector<SUnit *> PhysicalRegCopy;
InstKind CurInstKind;
int CurEmitted;
Modified: llvm/trunk/test/CodeGen/R600/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fabs.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fabs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fabs.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MOV * T{{[0-9]+\.[XYZW], \|PV\.[XYZW]\|}}
+;CHECK: MOV * T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fadd.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fadd.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fadd.ll Wed Jun 5 15:27:35 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @fadd_f32
-; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @fadd_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/floor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/floor.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/floor.ll (original)
+++ llvm/trunk/test/CodeGen/R600/floor.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: FLOOR * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fmad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmad.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmad.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmad.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], PV\.[XYZW], PV.[XYZW], PV\.[XYZW]}}
+;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmax.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmax.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmax.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MAX * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
+;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fmin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmin.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmin.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmin.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MIN * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
+;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmul.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmul.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmul.ll Wed Jun 5 15:27:35 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @fmul_f32
-; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
+; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @fmul_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/fsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsub.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsub.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsub.ll Wed Jun 5 15:27:35 2013
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @fsub_f32
-; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[XYZW], -PV\.[XYZW]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
define void @fsub_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.mul.ll Wed Jun 5 15:27:35 2013
@@ -1,6 +1,6 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
+;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
%r0 = call float @llvm.R600.load.input(i32 0)
Modified: llvm/trunk/test/CodeGen/R600/llvm.pow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.pow.ll?rev=183336&r1=183335&r2=183336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.pow.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.pow.ll Wed Jun 5 15:27:35 2013
@@ -1,7 +1,7 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test() {
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