[llvm] r183307 - This is a simple patch that changes RRX and RRXS to accept all registers as operands.

[Mihai Popa]

Author: mpopa
Date: Wed Jun  5 08:23:51 2013
New Revision: 183307

URL: http://llvm.org/viewvc/llvm-project?rev=183307&view=rev
Log:
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s
    llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=183307&r1=183306&r2=183307&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jun  5 08:23:51 2013
@@ -5233,7 +5233,7 @@ def RORi : ARMAsmPseudo<"ror${s}${p} $Rd
                              cc_out:$s)>;
 }
 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
-                        (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
+                        (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
                         (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=183307&r1=183306&r2=183307&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Jun  5 08:23:51 2013
@@ -1645,6 +1645,30 @@ Lforward:
 @ CHECK: rsc	r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0xe6,0xe0]
 
 @------------------------------------------------------------------------------
+@ RRX/RRXS
+ at ------------------------------------------------------------------------------
+
+         rrx r0, r1
+	 rrx sp, pc
+	 rrx pc, lr
+	 rrx lr, sp
+
+@ CHECK: rrx	r0, r1                  @ encoding: [0x61,0x00,0xa0,0xe1]
+@ CHECK: rrx	sp, pc                  @ encoding: [0x6f,0xd0,0xa0,0xe1]
+@ CHECK: rrx	pc, lr                  @ encoding: [0x6e,0xf0,0xa0,0xe1]
+@ CHECK: rrx	lr, sp                  @ encoding: [0x6d,0xe0,0xa0,0xe1]
+
+         rrxs r0, r1
+	 rrxs sp, pc
+	 rrxs pc, lr
+	 rrxs lr, sp
+
+ at CHECK: rrxs	r0, r1                  @ encoding: [0x61,0x00,0xb0,0xe1]
+ at CHECK: rrxs	sp, pc                  @ encoding: [0x6f,0xd0,0xb0,0xe1]
+ at CHECK: rrxs	pc, lr                  @ encoding: [0x6e,0xf0,0xb0,0xe1]
+ at CHECK: rrxs	lr, sp                  @ encoding: [0x6d,0xe0,0xb0,0xe1]
+
+@ ------------------------------------------------------------------------------
 @ SADD16/SADD8
 @------------------------------------------------------------------------------
         sadd16 r1, r2, r3

Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=183307&r1=183306&r2=183307&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Wed Jun  5 08:23:51 2013
@@ -1301,6 +1301,29 @@
 0x77 0x69 0xe6 0xe0
 
 #------------------------------------------------------------------------------
+# RRX/RRXS
+#------------------------------------------------------------------------------
+# CHECK: rrx	r0, r1
+# CHECK: rrx	sp, pc
+# CHECK: rrx	pc, lr
+# CHECK: rrx	lr, sp
+
+0x61 0x00 0xa0 0xe1
+0x6f 0xd0 0xa0 0xe1
+0x6e 0xf0 0xa0 0xe1
+0x6d 0xe0 0xa0 0xe1
+
+# CHECK: rrxs	r0, r1
+# CHECK: rrxs	sp, pc
+# CHECK: rrxs	pc, lr
+# CHECK: rrxs	lr, sp
+
+0x61 0x00 0xb0 0xe1
+0x6f 0xd0 0xb0 0xe1
+0x6e 0xf0 0xb0 0xe1
+0x6d 0xe0 0xb0 0xe1
+
+#------------------------------------------------------------------------------
 # SADD16/SADD8
 #------------------------------------------------------------------------------
 # CHECK: sadd16 r1, r2, r3