[llvm] r183273 - Revert series of sched model patches until I figure out what is going on.

Arnold Schwaighofer aschwaighofer at apple.com
Tue Jun 4 15:35:18 PDT 2013


Author: arnolds
Date: Tue Jun  4 17:35:17 2013
New Revision: 183273

URL: http://llvm.org/viewvc/llvm-project?rev=183273&view=rev
Log:
Revert series of sched model patches until I figure out what is going on.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/lib/Target/ARM/ARMSchedule.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
    llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun  4 17:35:17 2013
@@ -4152,8 +4152,6 @@ bool ARMBaseInstrInfo::hasNOP() const {
 }
 
 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
-  if (MI->getNumOperands() < 4)
-    return true;
   unsigned ShOpVal = MI->getOperand(3).getImm();
   unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
   // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun  4 17:35:17 2013
@@ -1327,7 +1327,7 @@ class AI_ext_rrot<bits<8> opcod, string
   : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
           IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
           [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
-       Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
+       Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rm;
   bits<2> rot;
@@ -1340,11 +1340,11 @@ class AI_ext_rrot<bits<8> opcod, string
 class AI_ext_rrot_np<bits<8> opcod, string opc>
   : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
           IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
-       Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
+       Requires<[IsARM, HasV6]> {
   bits<2> rot;
   let Inst{19-16} = 0b1111;
   let Inst{11-10} = rot;
- }
+}
 
 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
@@ -1353,7 +1353,7 @@ class AI_exta_rrot<bits<8> opcod, string
           IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
           [(set GPRnopc:$Rd, (opnode GPR:$Rn,
                                      (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
-        Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
+        Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rm;
   bits<4> Rn;
@@ -1368,7 +1368,7 @@ class AI_exta_rrot<bits<8> opcod, string
 class AI_exta_rrot_np<bits<8> opcod, string opc>
   : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
           IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
-       Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
+       Requires<[IsARM, HasV6]> {
   bits<4> Rn;
   bits<2> rot;
   let Inst{19-16} = Rn;
@@ -1780,8 +1780,7 @@ multiclass APreLoad<bits<1> read, bits<1
 
   def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
                 !strconcat(opc, "\t$addr"),
-                [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
-                Sched<[WritePreLd]> {
+                [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
     bits<4> Rt;
     bits<17> addr;
     let Inst{31-26} = 0b111101;
@@ -1797,8 +1796,7 @@ multiclass APreLoad<bits<1> read, bits<1
 
   def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
                !strconcat(opc, "\t$shift"),
-               [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
-               Sched<[WritePreLd]> {
+               [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
     bits<17> shift;
     let Inst{31-26} = 0b111101;
     let Inst{25} = 1; // 1 for register form
@@ -1865,8 +1863,7 @@ def TRAP : AXI<(outs), (ins), MiscFrm, N
 let isNotDuplicable = 1 in {
 def PICADD  : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
                             4, IIC_iALUr,
-                            [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
-                            Sched<[WriteALU, ReadALU]>;
+                            [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
 
 let AddedComplexity = 10 in {
 def PICLDR  : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
@@ -1926,11 +1923,11 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd),
 
 let hasSideEffects = 1 in {
 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
-                    4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
+                    4, IIC_iALUi, []>;
 
 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
                       (ins i32imm:$label, nohash_imm:$id, pred:$p),
-                      4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
+                      4, IIC_iALUi, []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1941,14 +1938,14 @@ let isReturn = 1, isTerminator = 1, isBa
   // ARMV4T and above
   def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
                   "bx", "\tlr", [(ARMretflag)]>,
-               Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
+               Requires<[IsARM, HasV4T]> {
     let Inst{27-0}  = 0b0001001011111111111100011110;
   }
 
   // ARMV4 only
   def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
                   "mov", "\tpc, lr", [(ARMretflag)]>,
-               Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
+               Requires<[IsARM, NoV4T]> {
     let Inst{27-0} = 0b0001101000001111000000001110;
   }
 }
@@ -1958,7 +1955,7 @@ let isBranch = 1, isTerminator = 1, isBa
   // ARMV4T and above
   def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
                   [(brind GPR:$dst)]>,
-              Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
+              Requires<[IsARM, HasV4T]> {
     bits<4> dst;
     let Inst{31-4} = 0b1110000100101111111111110001;
     let Inst{3-0}  = dst;
@@ -1966,7 +1963,7 @@ let isBranch = 1, isTerminator = 1, isBa
 
   def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
                   "bx", "\t$dst", [/* pattern left blank */]>,
-              Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
+              Requires<[IsARM, HasV4T]> {
     bits<4> dst;
     let Inst{27-4} = 0b000100101111111111110001;
     let Inst{3-0}  = dst;
@@ -1983,7 +1980,7 @@ let isCall = 1,
   def BL  : ABXI<0b1011, (outs), (ins bl_target:$func),
                 IIC_Br, "bl\t$func",
                 [(ARMcall tglobaladdr:$func)]>,
-            Requires<[IsARM]>, Sched<[WriteBrL]> {
+            Requires<[IsARM]> {
     let Inst{31-28} = 0b1110;
     bits<24> func;
     let Inst{23-0} = func;
@@ -1993,7 +1990,7 @@ let isCall = 1,
   def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
                    IIC_Br, "bl", "\t$func",
                    [(ARMcall_pred tglobaladdr:$func)]>,
-                Requires<[IsARM]>, Sched<[WriteBrL]> {
+                Requires<[IsARM]> {
     bits<24> func;
     let Inst{23-0} = func;
     let DecoderMethod = "DecodeBranchImmInstruction";
@@ -2003,7 +2000,7 @@ let isCall = 1,
   def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
                 IIC_Br, "blx\t$func",
                 [(ARMcall GPR:$func)]>,
-            Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
+            Requires<[IsARM, HasV5T]> {
     bits<4> func;
     let Inst{31-4} = 0b1110000100101111111111110011;
     let Inst{3-0}  = func;
@@ -2012,7 +2009,7 @@ let isCall = 1,
   def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
                     IIC_Br, "blx", "\t$func",
                     [(ARMcall_pred GPR:$func)]>,
-                 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
+                 Requires<[IsARM, HasV5T]> {
     bits<4> func;
     let Inst{27-4} = 0b000100101111111111110011;
     let Inst{3-0}  = func;
@@ -2022,18 +2019,18 @@ let isCall = 1,
   // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
   def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
                    8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
-                   Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
+                   Requires<[IsARM, HasV4T]>;
 
   // ARMv4
   def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
                    8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
-                   Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
+                   Requires<[IsARM, NoV4T]>;
 
   // mov lr, pc; b if callee is marked noreturn to avoid confusing the
   // return stack predictor.
   def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
                                8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
-                      Requires<[IsARM]>, Sched<[WriteBr]>;
+                      Requires<[IsARM]>;
 }
 
 let isBranch = 1, isTerminator = 1 in {
@@ -2041,8 +2038,7 @@ let isBranch = 1, isTerminator = 1 in {
   // a two-value operand where a dag node expects two operands. :(
   def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
                IIC_Br, "b", "\t$target",
-               [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
-               Sched<[WriteBr]>  {
+               [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
     bits<24> target;
     let Inst{23-0} = target;
     let DecoderMethod = "DecodeBranchImmInstruction";
@@ -2055,27 +2051,25 @@ let isBranch = 1, isTerminator = 1 in {
     // should be sufficient.
     // FIXME: Is B really a Barrier? That doesn't seem right.
     def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
-                [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
-                Sched<[WriteBr]>;
+                [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
 
     let isNotDuplicable = 1, isIndirectBranch = 1 in {
     def BR_JTr : ARMPseudoInst<(outs),
                       (ins GPR:$target, i32imm:$jt, i32imm:$id),
                       0, IIC_Br,
-                      [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
-                      Sched<[WriteBr]>;
+                      [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
     // FIXME: This shouldn't use the generic "addrmode2," but rather be split
     // into i12 and rs suffixed versions.
     def BR_JTm : ARMPseudoInst<(outs),
                      (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
                      0, IIC_Br,
                      [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
-                       imm:$id)]>, Sched<[WriteBrTbl]>;
+                       imm:$id)]>;
     def BR_JTadd : ARMPseudoInst<(outs),
                    (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
                    0, IIC_Br,
                    [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
-                     imm:$id)]>, Sched<[WriteBrTbl]>;
+                     imm:$id)]>;
     } // isNotDuplicable = 1, isIndirectBranch = 1
   } // isBarrier = 1
 
@@ -2084,7 +2078,7 @@ let isBranch = 1, isTerminator = 1 in {
 // BLX (immediate)
 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
                "blx\t$target", []>,
-           Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
+           Requires<[IsARM, HasV5T]> {
   let Inst{31-25} = 0b1111101;
   bits<25> target;
   let Inst{23-0} = target{24-1};
@@ -2093,7 +2087,7 @@ def BLXi : AXI<(outs), (ins blx_target:$
 
 // Branch and Exchange Jazelle
 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
-              [/* pattern left blank */]>, Sched<[WriteBr]> {
+              [/* pattern left blank */]> {
   bits<4> func;
   let Inst{23-20} = 0b0010;
   let Inst{19-8} = 0xfff;
@@ -2104,20 +2098,18 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$
 // Tail calls.
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
-  def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
-                   Sched<[WriteBr]>;
+  def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
 
-  def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
-                   Sched<[WriteBr]>;
+  def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
 
   def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
                                  4, IIC_Br, [],
                                  (Bcc br_target:$dst, (ops 14, zero_reg))>,
-                                 Requires<[IsARM]>, Sched<[WriteBr]>;
+                                 Requires<[IsARM]>;
 
   def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
                                  4, IIC_Br, [],
-                                 (BX GPR:$dst)>, Sched<[WriteBr]>,
+                                 (BX GPR:$dst)>,
                                  Requires<[IsARM]>;
 }
 
@@ -2131,8 +2123,7 @@ def SMC : ABI<0b0001, (outs), (ins imm0_
 
 // Supervisor Call (Software Interrupt)
 let isCall = 1, Uses = [SP] in {
-def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
-          Sched<[WriteBr]> {
+def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
   bits<24> svc;
   let Inst{23-0} = svc;
 }
@@ -2964,7 +2955,7 @@ defm sysSTM : arm_ldst_mult<"stm", " ^",
 
 let neverHasSideEffects = 1 in
 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
-                "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
+                "mov", "\t$Rd, $Rm", []>, UnaryDP {
   bits<4> Rd;
   bits<4> Rm;
 
@@ -2978,7 +2969,7 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd),
 // A version for the smaller set of tail call registers.
 let neverHasSideEffects = 1 in
 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
-                IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
+                IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
   bits<4> Rd;
   bits<4> Rm;
 
@@ -2991,8 +2982,7 @@ def MOVr_TC : AsI1<0b1101, (outs tcGPR:$
 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
                 DPSoRegRegFrm, IIC_iMOVsr,
                 "mov", "\t$Rd, $src",
-                [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
-                Sched<[WriteALU]> {
+                [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
   bits<4> Rd;
   bits<12> src;
   let Inst{15-12} = Rd;
@@ -3008,7 +2998,7 @@ def MOVsr : AsI1<0b1101, (outs GPRnopc:$
 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
                 DPSoRegImmFrm, IIC_iMOVsr,
                 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
-                UnaryDP, Sched<[WriteALU]> {
+                UnaryDP {
   bits<4> Rd;
   bits<12> src;
   let Inst{15-12} = Rd;
@@ -3021,8 +3011,7 @@ def MOVsi : AsI1<0b1101, (outs GPR:$Rd),
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
-                "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
-                Sched<[WriteALU]> {
+                "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
   bits<4> Rd;
   bits<12> imm;
   let Inst{25} = 1;
@@ -3036,7 +3025,7 @@ def MOVi16 : AI1<0b1000, (outs GPR:$Rd),
                  DPFrm, IIC_iMOVi,
                  "movw", "\t$Rd, $imm",
                  [(set GPR:$Rd, imm0_65535:$imm)]>,
-                 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
+                 Requires<[IsARM, HasV6T2]>, UnaryDP {
   bits<4> Rd;
   bits<16> imm;
   let Inst{15-12} = Rd;
@@ -3052,8 +3041,7 @@ def : InstAlias<"mov${p} $Rd, $imm",
         Requires<[IsARM]>;
 
 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
-                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
-                      Sched<[WriteALU]>;
+                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
 
 let Constraints = "$src = $Rd" in {
 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
@@ -3063,7 +3051,7 @@ def MOVTi16 : AI1<0b1010, (outs GPRnopc:
                   [(set GPRnopc:$Rd,
                         (or (and GPR:$src, 0xffff),
                             lo16AllZero:$imm))]>, UnaryDP,
-                  Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
+                  Requires<[IsARM, HasV6T2]> {
   bits<4> Rd;
   bits<16> imm;
   let Inst{15-12} = Rd;
@@ -3075,8 +3063,7 @@ def MOVTi16 : AI1<0b1010, (outs GPRnopc:
 }
 
 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
-                      (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
-                      Sched<[WriteALU]>;
+                      (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
 
 } // Constraints
 
@@ -3086,7 +3073,7 @@ def : ARMPat<(or GPR:$src, 0xffff0000),
 let Uses = [CPSR] in
 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
                     [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
-                    Requires<[IsARM]>, Sched<[WriteALU]>;
+                    Requires<[IsARM]>;
 
 // These aren't really mov instructions, but we have to define them this way
 // due to flag operands.
@@ -3094,10 +3081,10 @@ def RRX: PseudoInst<(outs GPR:$Rd), (ins
 let Defs = [CPSR] in {
 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
                       [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
-                      Sched<[WriteALU]>, Requires<[IsARM]>;
+                      Requires<[IsARM]>;
 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
                       [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
-                      Sched<[WriteALU]>, Requires<[IsARM]>;
+                      Requires<[IsARM]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -3263,8 +3250,7 @@ class AAI<bits<8> op27_20, bits<8> op11_
           list<dag> pattern = [],
           dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
           string asm = "\t$Rd, $Rn, $Rm">
-  : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
-    Sched<[WriteALU, ReadALU, ReadALU]> {
+  : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
   bits<4> Rn;
   bits<4> Rd;
   bits<4> Rm;
@@ -3340,7 +3326,7 @@ def UHSUB8  : AAI<0b01100111, 0b11111111
 def USAD8  : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
                 MulFrm /* for convenience */, NoItinerary, "usad8",
                 "\t$Rd, $Rn, $Rm", []>,
-             Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
+             Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rm;
@@ -3354,7 +3340,7 @@ def USAD8  : AI<(outs GPR:$Rd), (ins GPR
 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
                 MulFrm /* for convenience */, NoItinerary, "usada8",
                 "\t$Rd, $Rn, $Rm, $Ra", []>,
-             Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
+             Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rm;
@@ -3487,7 +3473,7 @@ def BFI:I<(outs GPRnopc:$Rd), (ins GPRno
 
 def  MVNr  : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
                   "mvn", "\t$Rd, $Rm",
-                  [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
+                  [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
   bits<4> Rd;
   bits<4> Rm;
   let Inst{25} = 0;
@@ -3498,8 +3484,7 @@ def  MVNr  : AsI1<0b1111, (outs GPR:$Rd)
 }
 def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
                   DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
-                  [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
-                  Sched<[WriteALU]> {
+                  [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
   bits<4> Rd;
   bits<12> shift;
   let Inst{25} = 0;
@@ -3511,8 +3496,7 @@ def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd
 }
 def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
                   DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
-                  [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
-                  Sched<[WriteALU]> {
+                  [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
   bits<4> Rd;
   bits<12> shift;
   let Inst{25} = 0;
@@ -3527,7 +3511,7 @@ def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
                   IIC_iMVNi, "mvn", "\t$Rd, $imm",
-                  [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
+                  [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
   bits<4> Rd;
   bits<12> imm;
   let Inst{25} = 1;
@@ -4038,8 +4022,7 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_reg_r
 let isCompare = 1, Defs = [CPSR] in {
 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
                 "cmn", "\t$Rn, $imm",
-                [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
-                Sched<[WriteCMP, ReadALU]> {
+                [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
   bits<4> Rn;
   bits<12> imm;
   let Inst{25} = 1;
@@ -4055,7 +4038,7 @@ def CMNri : AI1<0b1011, (outs), (ins GPR
 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
                  "cmn", "\t$Rn, $Rm",
                  [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
-                   GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
+                   GPR:$Rn, GPR:$Rm)]> {
   bits<4> Rn;
   bits<4> Rm;
   let isCommutable = 1;
@@ -4073,8 +4056,7 @@ def CMNzrsi : AI1<0b1011, (outs),
                   (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
                   "cmn", "\t$Rn, $shift",
                   [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
-                    GPR:$Rn, so_reg_imm:$shift)]>,
-                    Sched<[WriteCMPsi, ReadALU]> {
+                    GPR:$Rn, so_reg_imm:$shift)]> {
   bits<4> Rn;
   bits<12> shift;
   let Inst{25} = 0;
@@ -4092,8 +4074,7 @@ def CMNzrsr : AI1<0b1011, (outs),
                   (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
                   "cmn", "\t$Rn, $shift",
                   [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
-                    GPRnopc:$Rn, so_reg_reg:$shift)]>,
-                    Sched<[WriteCMPsr, ReadALU]> {
+                    GPRnopc:$Rn, so_reg_reg:$shift)]> {
   bits<4> Rn;
   bits<12> shift;
   let Inst{25} = 0;
@@ -4131,13 +4112,11 @@ let usesCustomInserter = 1, isBranch = 1
 def BCCi64 : PseudoInst<(outs),
     (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
      IIC_Br,
-    [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
-    Sched<[WriteBr]>;
+    [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
 
 def BCCZi64 : PseudoInst<(outs),
      (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
-    [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
-    Sched<[WriteBr]>;
+    [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
 } // usesCustomInserter
 
 
@@ -4150,20 +4129,20 @@ let isCommutable = 1, isSelect = 1 in
 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
                            4, IIC_iCMOVr,
   [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
-      RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+      RegConstraint<"$false = $Rd">;
 
 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
                            (ins GPR:$false, so_reg_imm:$shift, pred:$p),
                            4, IIC_iCMOVsr,
   [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
                             imm:$cc, CCR:$ccr))*/]>,
-      RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+      RegConstraint<"$false = $Rd">;
 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
                            (ins GPR:$false, so_reg_reg:$shift, pred:$p),
                            4, IIC_iCMOVsr,
   [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
                             imm:$cc, CCR:$ccr))*/]>,
-      RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+      RegConstraint<"$false = $Rd">;
 
 
 let isMoveImm = 1 in
@@ -4171,15 +4150,14 @@ def MOVCCi16 : ARMPseudoInst<(outs GPR:$
                              (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
                              4, IIC_iMOVi,
                              []>,
-      RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
-      Sched<[WriteALU]>;
+      RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
 
 let isMoveImm = 1 in
 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
                            (ins GPR:$false, so_imm:$imm, pred:$p),
                            4, IIC_iCMOVi,
    [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
-      RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+      RegConstraint<"$false = $Rd">;
 
 // Two instruction predicate mov immediate.
 let isMoveImm = 1 in
@@ -4192,7 +4170,7 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd
                            (ins GPR:$false, so_imm:$imm, pred:$p),
                            4, IIC_iCMOVi,
  [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
-                RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+                RegConstraint<"$false = $Rd">;
 
 } // neverHasSideEffects
 
@@ -4842,7 +4820,7 @@ def MSRi : ABI<0b0011, (outs), (ins msr_
 let isCall = 1,
   Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
   def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
-               [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
+               [(set R0, ARMthread_pointer)]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -4906,7 +4884,7 @@ let isBranch = 1, isTerminator = 1, isBa
   def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
                     4, IIC_Br, [(brind GPR:$dst)],
                     (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
-                  Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
+                  Requires<[IsARM, NoV4T]>;
 
 // Large immediate handling.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Jun  4 17:35:17 2013
@@ -310,7 +310,7 @@ def tCPS : T1I<(outs), (ins imod_op:$imo
 let isNotDuplicable = 1, isCodeGenOnly = 1 in
 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
                   [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
-              T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
+              T1Special<{0,0,?,?}> {
   // A8.6.6
   bits<3> dst;
   let Inst{6-3} = 0b1111; // Rm = pc
@@ -323,7 +323,7 @@ def tPICADD : TIt<(outs GPR:$dst), (ins
 // probably because the instruction can be moved around.
 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
                     IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
-               T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
+               T1Encoding<{1,0,1,0,1,?}> {
   // A6.2 & A8.6.8
   bits<3> dst;
   bits<8> imm;
@@ -335,7 +335,7 @@ def tADDrSPi : T1pI<(outs tGPR:$dst), (i
 // ADD sp, sp, #<imm7>
 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
                      IIC_iALUi, "add", "\t$Rdn, $imm", []>,
-              T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
+              T1Misc<{0,0,0,0,0,?,?}> {
   // A6.2.5 & A8.6.8
   bits<7> imm;
   let Inst{6-0} = imm;
@@ -346,7 +346,7 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (
 // FIXME: The encoding and the ASM string don't match up.
 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
                     IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
-              T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
+              T1Misc<{0,0,0,0,1,?,?}> {
   // A6.2.5 & A8.6.214
   bits<7> imm;
   let Inst{6-0} = imm;
@@ -367,7 +367,7 @@ def : tInstAlias<"sub${p} sp, sp, $imm",
 // ADD <Rm>, sp
 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
                    "add", "\t$Rdn, $sp, $Rn", []>,
-              T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
+              T1Special<{0,0,?,?}> {
   // A8.6.9 Encoding T1
   bits<4> Rdn;
   let Inst{7}   = Rdn{3};
@@ -379,7 +379,7 @@ def tADDrSP : T1pI<(outs GPR:$Rdn), (ins
 // ADD sp, <Rm>
 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
                   "add", "\t$Rdn, $Rm", []>,
-              T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
+              T1Special<{0,0,?,?}> {
   // A8.6.9 Encoding T2
   bits<4> Rm;
   let Inst{7} = 1;
@@ -395,7 +395,7 @@ def tADDspr : T1pIt<(outs GPRsp:$Rdn), (
 // Indirect branches
 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
   def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
-            T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
+            T1Special<{1,1,0,?}> {
     // A6.2.3 & A8.6.25
     bits<4> Rm;
     let Inst{6-3} = Rm;
@@ -406,12 +406,12 @@ let isBranch = 1, isTerminator = 1, isBa
 
 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
   def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
-                   [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
+                   [(ARMretflag)], (tBX LR, pred:$p)>;
 
   // Alternative return instruction used by vararg functions.
   def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
                    2, IIC_Br, [],
-                   (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
+                   (tBX GPR:$Rm, pred:$p)>;
 }
 
 // All calls clobber the non-callee saved registers. SP is marked as a use to
@@ -424,7 +424,7 @@ let isCall = 1,
                   (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
                   "bl${p}\t$func",
                   [(ARMtcall tglobaladdr:$func)]>,
-             Requires<[IsThumb]>, Sched<[WriteBrL]> {
+             Requires<[IsThumb]> {
     bits<24> func;
     let Inst{26} = func{23};
     let Inst{25-16} = func{20-11};
@@ -438,7 +438,7 @@ let isCall = 1,
                  (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
                    "blx${p}\t$func",
                    [(ARMcall tglobaladdr:$func)]>,
-              Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
+              Requires<[IsThumb, HasV5T]> {
     bits<24> func;
     let Inst{26} = func{23};
     let Inst{25-16} = func{20-11};
@@ -453,7 +453,7 @@ let isCall = 1,
                   "blx${p}\t$func",
                   [(ARMtcall GPR:$func)]>,
               Requires<[IsThumb, HasV5T]>,
-              T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
+              T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
     bits<4> func;
     let Inst{6-3} = func;
     let Inst{2-0} = 0b000;
@@ -463,14 +463,14 @@ let isCall = 1,
   def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
                   4, IIC_Br,
                   [(ARMcall_nolink tGPR:$func)]>,
-            Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
+            Requires<[IsThumb, IsThumb1Only]>;
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
   let isPredicable = 1 in
   def tB   : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
                  "b", "\t$target", [(br bb:$target)]>,
-             T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
+             T1Encoding<{1,1,1,0,0,?}> {
     bits<11> target;
     let Inst{10-0} = target;
   }
@@ -480,14 +480,12 @@ let isBranch = 1, isTerminator = 1, isBa
   // the clobber of LR.
   let Defs = [LR] in
   def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
-                          4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
-                          Sched<[WriteBrTbl]>;
+                          4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
 
   def tBR_JTr : tPseudoInst<(outs),
                       (ins tGPR:$target, i32imm:$jt, i32imm:$id),
                       0, IIC_Br,
-                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
-                      Sched<[WriteBrTbl]> {
+                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
     list<Predicate> Predicates = [IsThumb, IsThumb1Only];
   }
 }
@@ -498,7 +496,7 @@ let isBranch = 1, isTerminator = 1 in
   def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
                  "b${p}\t$target",
                  [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
-             T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
+             T1BranchCond<{1,1,0,1}> {
   bits<4> p;
   bits<8> target;
   let Inst{11-8} = p;
@@ -512,7 +510,7 @@ let isCall = 1, isTerminator = 1, isRetu
     def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
                      4, IIC_Br, [],
                      (tBX GPR:$dst, (ops 14, zero_reg))>,
-                     Requires<[IsThumb]>, Sched<[WriteBr]>;
+                     Requires<[IsThumb]>;
   }
   // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
   // on IOS), so it's in ARMInstrThumb2.td.
@@ -522,7 +520,7 @@ let isCall = 1, isTerminator = 1, isRetu
                    (ins t_brtarget:$dst, pred:$p),
                    4, IIC_Br, [],
                    (tB t_brtarget:$dst, pred:$p)>,
-                 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
+                 Requires<[IsThumb, IsNotIOS]>;
   }
 }
 
@@ -532,7 +530,7 @@ let isCall = 1, isTerminator = 1, isRetu
 // If Inst{11-8} == 0b1111 then SEE SVC
 let isCall = 1, Uses = [SP] in
 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
-                "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
+                "svc", "\t$imm", []>, Encoding16 {
   bits<8> imm;
   let Inst{15-12} = 0b1101;
   let Inst{11-8}  = 0b1111;
@@ -542,7 +540,7 @@ def tSVC : T1pI<(outs), (ins imm0_255:$i
 // The assembler uses 0xDEFE for a trap instruction.
 let isBarrier = 1, isTerminator = 1 in
 def tTRAP : TI<(outs), (ins), IIC_Br,
-               "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
+               "trap", [(trap)]>, Encoding16 {
   let Inst = 0xdefe;
 }
 
@@ -835,15 +833,14 @@ let isCommutable = 1, Uses = [CPSR] in
 def tADC :                      // A8.6.2
   T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
                 "adc", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
 
 // Add immediate
 def tADDi3 :                    // A8.6.4 T1
   T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                    IIC_iALUi,
                    "add", "\t$Rd, $Rm, $imm3",
-                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
-                   Sched<[WriteALU]> {
+                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
   bits<3> imm3;
   let Inst{8-6} = imm3;
 }
@@ -852,8 +849,7 @@ def tADDi8 :                    // A8.6.
   T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
                     (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                     "add", "\t$Rdn, $imm8",
-                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
-                    Sched<[WriteALU]>;
+                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
 
 // Add register
 let isCommutable = 1 in
@@ -861,12 +857,12 @@ def tADDrr :                    // A8.6.
   T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iALUr,
                 "add", "\t$Rd, $Rn, $Rm",
-                [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
 
 let neverHasSideEffects = 1 in
 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
                      "add", "\t$Rdn, $Rm", []>,
-               T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
+               T1Special<{0,0,?,?}> {
   // A8.6.6 T2
   bits<4> Rdn;
   bits<4> Rm;
@@ -881,15 +877,14 @@ def tAND :                      // A8.6.
   T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iBITr,
                 "and", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
 
 // ASR immediate
 def tASRri :                    // A8.6.14
   T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
                    IIC_iMOVsi,
                    "asr", "\t$Rd, $Rm, $imm5",
-                   [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
-                   Sched<[WriteALU]> {
+                   [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
   bits<5> imm5;
   let Inst{10-6} = imm5;
 }
@@ -899,15 +894,14 @@ def tASRrr :                    // A8.6.
   T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iMOVsr,
                 "asr", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
 
 // BIC register
 def tBIC :                      // A8.6.20
   T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iBITr,
                 "bic", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
-                Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
 
 // CMN register
 let isCompare = 1, Defs = [CPSR] in {
@@ -923,7 +917,7 @@ def tCMNz :                     // A8.6.
   T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
                IIC_iCMPr,
                "cmn", "\t$Rn, $Rm",
-               [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
+               [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
 
 } // isCompare = 1, Defs = [CPSR]
 
@@ -932,7 +926,7 @@ let isCompare = 1, Defs = [CPSR] in {
 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
                   "cmp", "\t$Rn, $imm8",
                   [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
-             T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
+             T1General<{1,0,1,?,?}> {
   // A8.6.35
   bits<3> Rn;
   bits<8> imm8;
@@ -945,11 +939,11 @@ def tCMPr :                     // A8.6.
   T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
                IIC_iCMPr,
                "cmp", "\t$Rn, $Rm",
-               [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
+               [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
 
 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
                    "cmp", "\t$Rn, $Rm", []>,
-              T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
+              T1Special<{0,1,?,?}> {
   // A8.6.36 T2
   bits<4> Rm;
   bits<4> Rn;
@@ -966,15 +960,14 @@ def tEOR :                      // A8.6.
   T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iBITr,
                 "eor", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
 
 // LSL immediate
 def tLSLri :                    // A8.6.88
   T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
                    IIC_iMOVsi,
                    "lsl", "\t$Rd, $Rm, $imm5",
-                   [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
-                   Sched<[WriteALU]> {
+                   [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
   bits<5> imm5;
   let Inst{10-6} = imm5;
 }
@@ -984,15 +977,14 @@ def tLSLrr :                    // A8.6.
   T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iMOVsr,
                 "lsl", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
 
 // LSR immediate
 def tLSRri :                    // A8.6.90
   T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
                    IIC_iMOVsi,
                    "lsr", "\t$Rd, $Rm, $imm5",
-                   [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
-                   Sched<[WriteALU]> {
+                   [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
   bits<5> imm5;
   let Inst{10-6} = imm5;
 }
@@ -1002,14 +994,14 @@ def tLSRrr :                    // A8.6.
   T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iMOVsr,
                 "lsr", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
 
 // Move register
 let isMoveImm = 1 in
 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
                   "mov", "\t$Rd, $imm8",
                   [(set tGPR:$Rd, imm0_255:$imm8)]>,
-             T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
+             T1General<{1,0,0,?,?}> {
   // A8.6.96
   bits<3> Rd;
   bits<8> imm8;
@@ -1027,7 +1019,7 @@ let neverHasSideEffects = 1 in {
 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
                       2, IIC_iMOVr,
                       "mov", "\t$Rd, $Rm", "", []>,
-                  T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
+                  T1Special<{1,0,?,?}> {
   // A8.6.97
   bits<4> Rd;
   bits<4> Rm;
@@ -1037,7 +1029,7 @@ def tMOVr : Thumb1pI<(outs GPR:$Rd), (in
 }
 let Defs = [CPSR] in
 def tMOVSr      : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
-                      "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
+                      "movs\t$Rd, $Rm", []>, Encoding16 {
   // A8.6.97
   bits<3> Rd;
   bits<3> Rm;
@@ -1068,7 +1060,7 @@ def :tInstAlias<"mul${s}${p} $Rdm, $Rn",
 def tMVN :                      // A8.6.107
   T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
                "mvn", "\t$Rd, $Rn",
-               [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
+               [(set tGPR:$Rd, (not tGPR:$Rn))]>;
 
 // Bitwise or register
 let isCommutable = 1 in
@@ -1076,7 +1068,7 @@ def tORR :                      // A8.6.
   T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iBITr,
                 "orr", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
 
 // Swaps
 def tREV :                      // A8.6.134
@@ -1084,36 +1076,35 @@ def tREV :                      // A8.6.
                  IIC_iUNAr,
                  "rev", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 def tREV16 :                    // A8.6.135
   T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
                  IIC_iUNAr,
                  "rev16", "\t$Rd, $Rm",
              [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
-                Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
+                Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 def tREVSH :                    // A8.6.136
   T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
                  IIC_iUNAr,
                  "revsh", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 // Rotate right register
 def tROR :                      // A8.6.139
   T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iMOVsr,
                 "ror", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
-                Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
 
 // Negate register
 def tRSB :                      // A8.6.141
   T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
                IIC_iALUi,
                "rsb", "\t$Rd, $Rn, #0",
-               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
+               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
 
 // Subtract with carry register
 let Uses = [CPSR] in
@@ -1121,16 +1112,14 @@ def tSBC :                      // A8.6.
   T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iALUr,
                 "sbc", "\t$Rdn, $Rm",
-                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
-                Sched<[WriteALU]>;
+                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
 
 // Subtract immediate
 def tSUBi3 :                    // A8.6.210 T1
   T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
                    IIC_iALUi,
                    "sub", "\t$Rd, $Rm, $imm3",
-                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
-                   Sched<[WriteALU]> {
+                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
   bits<3> imm3;
   let Inst{8-6} = imm3;
 }
@@ -1139,16 +1128,14 @@ def tSUBi8 :                    // A8.6.
   T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
                     (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                     "sub", "\t$Rdn, $imm8",
-                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
-                    Sched<[WriteALU]>;
+                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
 
 // Subtract register
 def tSUBrr :                    // A8.6.212
   T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
                 IIC_iALUr,
                 "sub", "\t$Rd, $Rn, $Rm",
-                [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
-                Sched<[WriteALU]>;
+                [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
 
 // Sign-extend byte
 def tSXTB :                     // A8.6.222
@@ -1156,8 +1143,7 @@ def tSXTB :                     // A8.6.
                  IIC_iUNAr,
                  "sxtb", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>,
-                 Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 // Sign-extend short
 def tSXTH :                     // A8.6.224
@@ -1165,16 +1151,14 @@ def tSXTH :                     // A8.6.
                  IIC_iUNAr,
                  "sxth", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>,
-                 Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 // Test
 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
 def tTST :                      // A8.6.230
   T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
                "tst", "\t$Rn, $Rm",
-               [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
-               Sched<[WriteALU]>;
+               [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
 
 // Zero-extend byte
 def tUXTB :                     // A8.6.262
@@ -1182,8 +1166,7 @@ def tUXTB :                     // A8.6.
                  IIC_iUNAr,
                  "uxtb", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>,
-                 Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 // Zero-extend short
 def tUXTH :                     // A8.6.264
@@ -1191,7 +1174,7 @@ def tUXTH :                     // A8.6.
                  IIC_iUNAr,
                  "uxth", "\t$Rd, $Rm",
                  [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
-                 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
+                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
 // Expanded after instruction selection into a branch sequence.
@@ -1206,7 +1189,7 @@ let usesCustomInserter = 1 in  // Expand
 
 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
                IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
-               T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
+               T1Encoding<{1,0,1,0,0,?}> {
   bits<3> Rd;
   bits<8> addr;
   let Inst{10-8} = Rd;
@@ -1216,12 +1199,12 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_a
 
 let neverHasSideEffects = 1, isReMaterializable = 1 in
 def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
-                              2, IIC_iALUi, []>, Sched<[WriteALU]>;
+                              2, IIC_iALUi, []>;
 
 let hasSideEffects = 1 in
 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
                               (ins i32imm:$label, nohash_imm:$id, pred:$p),
-                              2, IIC_iALUi, []>, Sched<[WriteALU]>;
+                              2, IIC_iALUi, []>;
 
 //===----------------------------------------------------------------------===//
 // TLS Instructions
@@ -1232,8 +1215,7 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR
 // complete with fixup for the aeabi_read_tp function.
 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
-                          [(set R0, ARMthread_pointer)]>,
-                          Sched<[WriteBr]>;
+                          [(set R0, ARMthread_pointer)]>;
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
@@ -1399,13 +1381,13 @@ let isReturn = 1, isTerminator = 1, isBa
     hasExtraDefRegAllocReq = 1 in
 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
                            2, IIC_iPop_Br, [],
-                           (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
+                           (tPOP pred:$p, reglist:$regs)>;
 
 // Indirect branch using "mov pc, $Rm"
 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
   def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
                   2, IIC_Br, [(brind GPR:$Rm)],
-                  (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
+                  (tMOVr PC, GPR:$Rm, pred:$p)>;
 }
 
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun  4 17:35:17 2013
@@ -554,8 +554,7 @@ multiclass T2I_bin_irs<bits<4> opcod, st
    def ri : T2sTwoRegImm<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
                  opc, "\t$Rd, $Rn, $imm",
-                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
-                 Sched<[WriteALU, ReadALU]> {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
@@ -564,8 +563,7 @@ multiclass T2I_bin_irs<bits<4> opcod, st
    // register
    def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
                  opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
-                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
-                 Sched<[WriteALU, ReadALU, ReadALU]> {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
      let isCommutable = Commutable;
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
@@ -578,8 +576,7 @@ multiclass T2I_bin_irs<bits<4> opcod, st
    def rs : T2sTwoRegShiftedReg<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
                  opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
-                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
-                 Sched<[WriteALUsi, ReadALU]>  {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -638,8 +635,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, s
    def ri : T2sTwoRegImm<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
                  opc, ".w\t$Rd, $Rn, $imm",
-                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
-                 Sched<[WriteALU, ReadALU]> {
+                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
@@ -649,8 +645,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, s
    def rr : T2sThreeReg<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
                  opc, "\t$Rd, $Rn, $Rm",
-                 [/* For disassembly only; pattern left blank */]>,
-                 Sched<[WriteALU, ReadALU, ReadALU]> {
+                 [/* For disassembly only; pattern left blank */]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -662,8 +657,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, s
    def rs : T2sTwoRegShiftedReg<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
                  IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
-                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
-                 Sched<[WriteALUsi, ReadALU]> {
+                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -684,14 +678,12 @@ multiclass T2I_bin_s_irs<InstrItinClass
                          (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
                          4, iii,
                          [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
-                                                t2_so_imm:$imm))]>,
-            Sched<[WriteALU, ReadALU]>;
+                                                t2_so_imm:$imm))]>;
    // register
    def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
                          4, iir,
                          [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
-                                                rGPR:$Rm))]>,
-            Sched<[WriteALU, ReadALU, ReadALU]> {
+                                                rGPR:$Rm))]> {
      let isCommutable = Commutable;
    }
    // shifted register
@@ -699,8 +691,7 @@ multiclass T2I_bin_s_irs<InstrItinClass
                          (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
                          4, iis,
                          [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
-                                                t2_so_reg:$ShiftedRm))]>,
-            Sched<[WriteALUsi, ReadALUsr]>;
+                                                t2_so_reg:$ShiftedRm))]>;
 }
 }
 
@@ -713,15 +704,13 @@ multiclass T2I_rbin_s_is<PatFrag opnode>
                          (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
                          4, IIC_iALUi,
                          [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
-                                                rGPR:$Rn))]>,
-            Sched<[WriteALU, ReadALU]>;
+                                                rGPR:$Rn))]>;
    // shifted register
    def rs : t2PseudoInst<(outs rGPR:$Rd),
                          (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
                          4, IIC_iALUsi,
                          [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
-                                                rGPR:$Rn))]>,
-            Sched<[WriteALUsi, ReadALU]>;
+                                                rGPR:$Rn))]>;
 }
 }
 
@@ -736,8 +725,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_2
    def ri : T2sTwoRegImm<
                (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
                opc, ".w\t$Rd, $Rn, $imm",
-               [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
-               Sched<[WriteALU, ReadALU]> {
+               [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24} = 1;
@@ -749,8 +737,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_2
    def ri12 : T2I<
                   (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
                   !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
-                  [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
-                  Sched<[WriteALU, ReadALU]> {
+                  [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
      bits<4> Rd;
      bits<4> Rn;
      bits<12> imm;
@@ -768,8 +755,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_2
    // register
    def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
                  IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
-                 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
-                 Sched<[WriteALU, ReadALU, ReadALU]> {
+                 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
      let isCommutable = Commutable;
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
@@ -783,8 +769,7 @@ multiclass T2I_bin_ii12rs<bits<3> op23_2
    def rs : T2sTwoRegShiftedReg<
                  (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
                  IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
-              [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
-              Sched<[WriteALUsi, ReadALU]> {
+              [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24} = 1;
@@ -802,7 +787,7 @@ multiclass T2I_adde_sube_irs<bits<4> opc
    def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
                  IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
                [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
-                 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
+                 Requires<[IsThumb2]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
@@ -812,7 +797,7 @@ multiclass T2I_adde_sube_irs<bits<4> opc
    def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
                  opc, ".w\t$Rd, $Rn, $Rm",
                  [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
-                 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
+                 Requires<[IsThumb2]> {
      let isCommutable = Commutable;
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
@@ -826,7 +811,7 @@ multiclass T2I_adde_sube_irs<bits<4> opc
                  (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
                  IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
          [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
-                 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
+                 Requires<[IsThumb2]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -841,8 +826,7 @@ multiclass T2I_sh_ir<bits<2> opcod, stri
    def ri : T2sTwoRegShiftImm<
                  (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
                  opc, ".w\t$Rd, $Rm, $imm",
-                 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
-                 Sched<[WriteALU]> {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-21} = 0b010010;
      let Inst{19-16} = 0b1111; // Rn
@@ -852,8 +836,7 @@ multiclass T2I_sh_ir<bits<2> opcod, stri
    def rr : T2sThreeReg<
                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
                  opc, ".w\t$Rd, $Rn, $Rm",
-                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
-                 Sched<[WriteALU]> {
+                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
      let Inst{31-27} = 0b11111;
      let Inst{26-23} = 0b0100;
      let Inst{22-21} = opcod;
@@ -897,7 +880,7 @@ let isCompare = 1, Defs = [CPSR] in {
    def ri : T2OneRegCmpImm<
                 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
                 opc, ".w\t$Rn, $imm",
-                [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
+                [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
@@ -909,7 +892,7 @@ let isCompare = 1, Defs = [CPSR] in {
    def rr : T2TwoRegCmp<
                 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
                 opc, ".w\t$Rn, $Rm",
-                [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
+                [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -923,8 +906,7 @@ let isCompare = 1, Defs = [CPSR] in {
    def rs : T2OneRegCmpShiftedReg<
                 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
                 opc, ".w\t$Rn, $ShiftedRm",
-                [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
-                Sched<[WriteCMPsi]> {
+                [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -1185,8 +1167,7 @@ class T2PCOneRegImm<dag oops, dag iops,
 // assembler.
 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
               (ins t2adrlabel:$addr, pred:$p),
-              IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
-              Sched<[WriteALU, ReadALU]> {
+              IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25-24} = 0b10;
   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@@ -1209,12 +1190,12 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd
 
 let neverHasSideEffects = 1, isReMaterializable = 1 in
 def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
-                                4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
+                                4, IIC_iALUi, []>;
 let hasSideEffects = 1 in
 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
                                 (ins i32imm:$label, nohash_imm:$id, pred:$p),
                                 4, IIC_iALUi,
-                                []>, Sched<[WriteALU, ReadALU]>;
+                                []>;
 
 
 //===----------------------------------------------------------------------===//
@@ -1539,8 +1520,7 @@ multiclass T2Ipl<bits<1> write, bits<1>
 
   def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
                 "\t$addr",
-              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
-              Sched<[WritePreLd]> {
+              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
     let Inst{31-25} = 0b1111100;
     let Inst{24} = instr;
     let Inst{22} = 0;
@@ -1557,8 +1537,7 @@ multiclass T2Ipl<bits<1> write, bits<1>
 
   def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
                 "\t$addr",
-            [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
-            Sched<[WritePreLd]> {
+            [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
     let Inst{31-25} = 0b1111100;
     let Inst{24} = instr;
     let Inst{23} = 0; // U = 0
@@ -1575,8 +1554,7 @@ multiclass T2Ipl<bits<1> write, bits<1>
 
   def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
                "\t$addr",
-             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
-             Sched<[WritePreLd]> {
+             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
     let Inst{31-25} = 0b1111100;
     let Inst{24} = instr;
     let Inst{23} = 0; // add = TRUE for T1
@@ -1765,7 +1743,7 @@ defm t2STM : thumb2_st_mult<"stm", IIC_i
 
 let neverHasSideEffects = 1 in
 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
-                   "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
+                   "mov", ".w\t$Rd, $Rm", []> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
@@ -1785,7 +1763,7 @@ let isReMaterializable = 1, isAsCheapAsA
     AddedComplexity = 1 in
 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
                    "mov", ".w\t$Rd, $imm",
-                   [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
+                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 0;
   let Inst{24-21} = 0b0010;
@@ -1808,7 +1786,7 @@ def : t2InstAlias<"mov${p} $Rd, $imm", (
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
                    "movw", "\t$Rd, $imm",
-                   [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
+                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-21} = 0b0010;
@@ -1834,8 +1812,7 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),
                     (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
                     "movt", "\t$Rd, $imm",
                     [(set rGPR:$Rd,
-                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
-                          Sched<[WriteALU]> {
+                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-21} = 0b0110;
@@ -1854,8 +1831,7 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd),
 }
 
 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
-                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
-                     Sched<[WriteALU]>;
+                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
 } // Constraints
 
 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
@@ -2195,7 +2171,7 @@ def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$
 let Uses = [CPSR] in {
 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
                    "rrx", "\t$Rd, $Rm",
-                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
+                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
@@ -2209,8 +2185,7 @@ let isCodeGenOnly = 1, Defs = [CPSR] in
 def t2MOVsrl_flag : T2TwoRegShiftImm<
                         (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
                         "lsrs", ".w\t$Rd, $Rm, #1",
-                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
-                        Sched<[WriteALU]> {
+                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
@@ -2224,8 +2199,7 @@ def t2MOVsrl_flag : T2TwoRegShiftImm<
 def t2MOVsra_flag : T2TwoRegShiftImm<
                         (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
                         "asrs", ".w\t$Rd, $Rm, #1",
-                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
-                        Sched<[WriteALU]> {
+                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
@@ -2346,7 +2320,7 @@ multiclass T2I_un_irs<bits<4> opcod, str
    // shifted imm
    def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
                 opc, "\t$Rd, $imm",
-                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
+                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
      let isAsCheapAsAMove = Cheap;
      let isReMaterializable = ReMat;
      let isMoveImm = MoveImm;
@@ -2359,7 +2333,7 @@ multiclass T2I_un_irs<bits<4> opcod, str
    // register
    def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
                 opc, ".w\t$Rd, $Rm",
-                [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
+                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -2371,8 +2345,7 @@ multiclass T2I_un_irs<bits<4> opcod, str
    // shifted register
    def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
                 opc, ".w\t$Rd, $ShiftedRm",
-                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
-                Sched<[WriteALU]> {
+                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -2831,27 +2804,22 @@ class T2I_misc<bits<2> op1, bits<2> op2,
 }
 
 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
-                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
-                    Sched<[WriteALU]>;
+                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
 
 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
                       "rbit", "\t$Rd, $Rm",
-                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
-                      Sched<[WriteALU]>;
+                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
 
 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
-                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
-                 Sched<[WriteALU]>;
+                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
 
 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
                        "rev16", ".w\t$Rd, $Rm",
-                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
-                Sched<[WriteALU]>;
+                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
 
 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
                        "revsh", ".w\t$Rd, $Rm",
-                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
-                 Sched<[WriteALU]>;
+                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
 
 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
                 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
@@ -2863,8 +2831,7 @@ def t2PKHBT : T2ThreeReg<
                   [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
                                       (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
                                            0xFFFF0000)))]>,
-                  Requires<[HasT2ExtractPack, IsThumb2]>,
-                  Sched<[WriteALUsi, ReadALU]> {
+                  Requires<[HasT2ExtractPack, IsThumb2]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-20} = 0b01100;
@@ -2892,8 +2859,7 @@ def t2PKHTB : T2ThreeReg<
                   [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
                                        (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
                                             0xFFFF)))]>,
-                  Requires<[HasT2ExtractPack, IsThumb2]>,
-                  Sched<[WriteALUsi, ReadALU]> {
+                  Requires<[HasT2ExtractPack, IsThumb2]> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-20} = 0b01100;
@@ -2934,8 +2900,7 @@ let isCompare = 1, Defs = [CPSR] in {
    def t2CMNri : T2OneRegCmpImm<
                 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
                 "cmn", ".w\t$Rn, $imm",
-                [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
-                Sched<[WriteCMP, ReadALU]> {
+                [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = 0b1000;
@@ -2948,7 +2913,7 @@ let isCompare = 1, Defs = [CPSR] in {
                 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
                 "cmn", ".w\t$Rn, $Rm",
                 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
-                  GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
+                  GPRnopc:$Rn, rGPR:$Rm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = 0b1000;
@@ -2963,8 +2928,7 @@ let isCompare = 1, Defs = [CPSR] in {
                 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
                 "cmn", ".w\t$Rn, $ShiftedRm",
                 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
-                  GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
-                  Sched<[WriteCMPsi, ReadALU, ReadALU]> {
+                  GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = 0b1000;
@@ -3004,15 +2968,14 @@ def t2MOVCCr : t2PseudoInst<(outs rGPR:$
                             (ins rGPR:$false, rGPR:$Rm, pred:$p),
                             4, IIC_iCMOVr,
    [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
-                RegConstraint<"$false = $Rd">,
-                Sched<[WriteALU]>;
+                RegConstraint<"$false = $Rd">;
 
 let isMoveImm = 1 in
 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
                             (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
                    4, IIC_iCMOVi,
 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
-                   RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
+                   RegConstraint<"$false = $Rd">;
 
 // FIXME: Pseudo-ize these. For now, just mark codegen only.
 let isCodeGenOnly = 1 in {
@@ -3020,7 +2983,7 @@ let isMoveImm = 1 in
 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
                       IIC_iCMOVi,
                       "movw", "\t$Rd, $imm", []>,
-                      RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
+                      RegConstraint<"$false = $Rd"> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-21} = 0b0010;
@@ -3047,7 +3010,7 @@ def t2MVNCCi : T2OneRegImm<(outs rGPR:$R
                    IIC_iCMOVi, "mvn", "\t$Rd, $imm",
 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
                    imm:$cc, CCR:$ccr))*/]>,
-                   RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
+                   RegConstraint<"$false = $Rd"> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 0;
   let Inst{24-21} = 0b0011;
@@ -3058,7 +3021,7 @@ def t2MVNCCi : T2OneRegImm<(outs rGPR:$R
 
 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
                    string opc, string asm, list<dag> pattern>
-  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern>, Sched<[WriteALU]> {
+  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
   let Inst{24-21} = 0b0010;
@@ -3280,7 +3243,7 @@ let isBranch = 1, isTerminator = 1, isBa
 let isPredicable = 1 in
 def t2B   : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
                  "b", ".w\t$target",
-                 [(br bb:$target)]>, Sched<[WriteBr]> {
+                 [(br bb:$target)]> {
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 1;
@@ -3298,20 +3261,17 @@ let isNotDuplicable = 1, isIndirectBranc
 def t2BR_JT : t2PseudoInst<(outs),
           (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
            0, IIC_Br,
-          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
-          Sched<[WriteBr]>;
+          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
 
 // FIXME: Add a non-pc based case that can be predicated.
 def t2TBB_JT : t2PseudoInst<(outs),
-        (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
-        Sched<[WriteBr]>;
+        (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
 
 def t2TBH_JT : t2PseudoInst<(outs),
-        (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
-        Sched<[WriteBr]>;
+        (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
 
 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
-                    "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
+                    "tbb", "\t$addr", []> {
   bits<4> Rn;
   bits<4> Rm;
   let Inst{31-20} = 0b111010001101;
@@ -3324,7 +3284,7 @@ def t2TBB : T2I<(outs), (ins addrmode_tb
 }
 
 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
-                   "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
+                   "tbh", "\t$addr", []> {
   bits<4> Rn;
   bits<4> Rm;
   let Inst{31-20} = 0b111010001101;
@@ -3344,7 +3304,7 @@ def t2TBH : T2I<(outs), (ins addrmode_tb
 let isBranch = 1, isTerminator = 1 in
 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
                 "b", ".w\t$target",
-                [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
+                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 0;
@@ -3371,7 +3331,7 @@ let isCall = 1, isTerminator = 1, isRetu
                    (ins uncondbrtarget:$dst, pred:$p),
                    4, IIC_Br, [],
                    (t2B uncondbrtarget:$dst, pred:$p)>,
-                 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
+                 Requires<[IsThumb2, IsIOS]>;
 }
 
 // IT block
@@ -3393,8 +3353,7 @@ def t2IT : Thumb2XI<(outs), (ins it_pred
 
 // Branch and Exchange Jazelle -- for disassembly only
 // Rm = Inst{19-16}
-def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
-    Sched<[WriteBr]> {
+def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
   bits<4> func;
   let Inst{31-27} = 0b11110;
   let Inst{26} = 0;
@@ -3408,7 +3367,7 @@ let isBranch = 1, isTerminator = 1 in {
   def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
                   "cbz\t$Rn, $target", []>,
               T1Misc<{0,0,?,1,?,?,?}>,
-              Requires<[IsThumb2]>, Sched<[WriteBr]> {
+              Requires<[IsThumb2]> {
     // A8.6.27
     bits<6> target;
     bits<3> Rn;
@@ -3420,7 +3379,7 @@ let isBranch = 1, isTerminator = 1 in {
   def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
                   "cbnz\t$Rn, $target", []>,
               T1Misc<{1,0,?,1,?,?,?}>,
-              Requires<[IsThumb2]>, Sched<[WriteBr]> {
+              Requires<[IsThumb2]> {
     // A8.6.27
     bits<6> target;
     bits<3> Rn;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Jun  4 17:35:17 2013
@@ -870,8 +870,7 @@ let Constraints = "$a = $dst" in {
 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
                           bit op5, dag oops, dag iops, InstrItinClass itin,
                           string opc, string asm, list<dag> pattern>
-  : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
-  Sched<[WriteCvtFP]> {
+  : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
   bits<5> dst;
   // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
   let Inst{22} = dst{0};
@@ -882,8 +881,7 @@ class AVConv1XInsS_Encode<bits<5> op1, b
 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
                           bit op5, dag oops, dag iops, InstrItinClass itin,
                           string opc, string asm, list<dag> pattern>
-  : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
-    Sched<[WriteCvtFP]> {
+  : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
   bits<5> dst;
   // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
   let Inst{22} = dst{4};

Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Tue Jun  4 17:35:17 2013
@@ -69,21 +69,6 @@ def WriteCMP : SchedWrite;
 def WriteCMPsi : SchedWrite;
 def WriteCMPsr : SchedWrite;
 
-// Division.
-def WriteDiv : SchedWrite;
-
-// Loads.
-def WriteLd : SchedWrite;
-def WritePreLd : SchedWrite;
-
-// Branches.
-def WriteBr : SchedWrite;
-def WriteBrL : SchedWrite;
-def WriteBrTbl : SchedWrite;
-
-// Fixpoint conversions.
-def WriteCvtFP : SchedWrite;
-
 // Define TII for use in SchedVariant Predicates.
 def : PredicateProlog<[{
   const ARMBaseInstrInfo *TII =

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Tue Jun  4 17:35:17 2013
@@ -2275,10 +2275,10 @@ def A9Read4 : SchedReadAdvance<3>;
 // This table follows the ARM Cortex-A9 Technical Reference Manuals,
 // mostly in order.
 
-def :ItinRW<[WriteALU], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
+def :ItinRW<[A9WriteI], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
                          IIC_iMVNi,IIC_iMVNsi,
                          IIC_iCMOVi,IIC_iCMOVr,IIC_iCMOVsi]>;
-def :ItinRW<[WriteALU, A9ReadALU],[IIC_iMVNr]>;
+def :ItinRW<[A9WriteI,A9ReadALU],[IIC_iMVNr]>;
 def :ItinRW<[A9WriteIsr], [IIC_iMOVsr,IIC_iMVNsr,IIC_iCMOVsr]>;
 
 def :ItinRW<[A9WriteI2],   [IIC_iMOVix2,IIC_iCMOVix2]>;
@@ -2487,58 +2487,10 @@ def : SchedAlias<WriteALUsr, A9WriteALUs
 def : SchedAlias<WriteALUSsr, A9WriteALUsr>;
 def : SchedAlias<ReadALU, A9ReadALU>;
 def : SchedAlias<ReadALUsr, A9ReadALU>;
-def : InstRW< [WriteALU],
-      (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr",
-                 "BICrr")>;
-def : InstRW< [WriteALUsi], (instregex "ANDrsi", "ORRrsi", "EORrsi", "BICrsi")>;
-def : InstRW< [WriteALUsr], (instregex "ANDrsr", "ORRrsr", "EORrsr", "BICrsr")>;
-
+// FIXME: need to special case AND, ORR, EOR, BIC because they don't read
+// advance. But our instrinfo claims it does.
 
 def : SchedAlias<WriteCMP, A9WriteALU>;
 def : SchedAlias<WriteCMPsi, A9WriteALU>;
 def : SchedAlias<WriteCMPsr, A9WriteALU>;
-
-def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi",
-                                       "MOVCCsr")>;
-def : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>;
-def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm",
-                                      "MOV_ga_dyn")>;
-def : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>;
-def : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>;
-
-def : InstRW< [WriteALU], (instregex "SEL")>;
-
-def : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>;
-
-def : InstRW< [A9WriteM],
-      (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
-      "SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>;
-def : InstRW< [A9WriteM, A9WriteMHi],
-      (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
-      "UMAAL", "SMLALv5", "UMLALv5", "UMAALv5", "SMLALBB", "SMLALBT", "SMLALTB",
-      "SMLALTT")>;
-// FIXME: These instructions used to have NoItinerary. Just copied the one from above.
-def : InstRW< [A9WriteM, A9WriteMHi],
-      (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX",
-      "SMLSLD", "SMLLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
-
-def : InstRW<[A9WriteM16, A9WriteM16Hi],
-      (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>;
-def : InstRW<[A9WriteM16, A9WriteM16Hi],
-      (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT")>;
-
-def : InstRW<[A9WriteL], (instregex "LDRi12", "PICLDR$")>;
-def : InstRW<[A9WriteLsi], (instregex "LDRrs")>;
-def : InstRW<[A9WriteLb],
-      (instregex "LDRBi12", "PICLDRH", "PICLDRB", "PICLDRSH", "PICLDRSB",
-      "LDRH", "LDRSH", "LDRSB")>;
-def : InstRW<[A9WriteLbsi], (instregex "LDRrs")>;
-
-def : WriteRes<WriteDiv, []> { let Latency = 0; }
-
-def : WriteRes<WriteBr, [A9UnitB]>;
-def : WriteRes<WriteBrL, [A9UnitB]>;
-def : WriteRes<WriteBrTbl, [A9UnitB]>;
-def : WriteRes<WritePreLd, []>;
-def : SchedAlias<WriteCvtFP, A9WriteF>;
 } // SchedModel = CortexA9Model

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td Tue Jun  4 17:35:17 2013
@@ -1096,27 +1096,9 @@ let SchedModel = SwiftModel in {
   def SwiftUnitDiv : ProcResource<1>;
 
   // Generic resource requirements.
-  def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>;
-  def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; }
-  def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; }
-  def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; }
-  def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
-    let Latency = 4;
-  }
-  def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
-    let Latency = 6;
-  }
-  def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>;
-  def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; }
-  def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; }
-  def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; }
-  def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; }
-  def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; }
-  def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>;
-  def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>;
   def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; }
-  def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01,
-                                                      SwiftUnitP01]> {
+  def SwiftWriteP01ThreeCycleTwoUops :
+    SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]> {
     let Latency = 3;
     let NumMicroOps = 2;
   }
@@ -1125,23 +1107,7 @@ let SchedModel = SwiftModel in {
     let NumMicroOps = 3;
     let ResourceCycles = [3];
   }
-  // Plain load without writeback.
-  def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
-    let Latency = 3;
-  }
-  def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> {
-    let Latency = 4;
-  }
-  // A store does not write to a register.
-  def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> {
-    let Latency = 0;
-  }
-  foreach Num = 1-4 in {
-    def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>;
-  }
-  def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle,
-                                                    SwiftWriteP01OneCycle,
-                                                    SwiftWriteP2ThreeCycle]>;
+
   // 4.2.4 Arithmetic and Logical.
   // ALU operation register shifted by immediate variant.
   def SwiftWriteALUsi : SchedWriteVariant<[
@@ -1171,896 +1137,8 @@ let SchedModel = SwiftModel in {
   def : ReadAdvance<ReadALU, 0>;
   def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>;
 
-
-  def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[
-    SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01OneCycle]>,
-    SchedVar<NoSchedPred,             [SwiftWriteP01TwoCycle]>
-  ]>;
-
   // 4.2.5 Integer comparison
   def : WriteRes<WriteCMP, [SwiftUnitP01]>;
-  def : SchedAlias<WriteCMPsi, SwiftChooseShiftKindP01OneOrTwoCycle>;
-  def : SchedAlias<WriteCMPsr, SwiftWriteP01TwoCycle>;
-
-  // 4.2.6 Shift, Move
-  // Shift
-  //  ASR,LSL,ROR,RRX
-  //  MOV(register-shiftedregister)  MVN(register-shiftedregister)
-  // Move
-  //  MOV,MVN
-  //  MOVT
-  // Sign/Zero extension
-  def : InstRW<[SwiftWriteP01OneCycle],
-               (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
-                          "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH",
-                          "t2UXTB16")>;
-  // Pseudo instructions.
-  def : InstRW<[SwiftWriteP01OneCycle2x],
-        (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi32imm",
-                   "t2MOVi32imm", "t2MOV_ga_dyn")>;
-  def : InstRW<[SwiftWriteP01OneCycle3x],
-        (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>;
-  def : InstRW<[SwiftWriteP01OneCycle2x_load],
-        (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
-
-  def SwiftWriteP0TwoCyleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
-
-  def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[
-    SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCyleTwoUops ]>,
-    SchedVar<NoSchedPred,     [ SwiftWriteP0OneCycle ]>
-  ]>;
-
-  // 4.2.7 Select
-  // SEL
-  def : InstRW<[SwiftPredP0OneOrTwoCycle], (instregex "SEL", "t2SEL")>;
-
-  // 4.2.8 Bitfield
-  // BFI,BFC, SBFX,UBFX
-  def : InstRW< [SwiftWriteP01TwoCycle],
-        (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
-        "(t|t2)UBFX", "(t|t2)SBFX")>;
-
-  // 4.2.9 Saturating arithmetic
-  def : InstRW< [SwiftWriteP01TwoCycle],
-        (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT",
-        "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX",
-        "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD",
-        "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT",
-        "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX",
-        "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX")>;
-
-  // 4.2.10 Parallel Arithmetic
-  // Not flag setting.
-  def : InstRW< [SwiftWriteALUsr],
-        (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX",
-        "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8",
-        "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8",
-        "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>;
-  // Flag setting.
-  def : InstRW< [SwiftWriteP01TwoCycle],
-       (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX",
-       "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16",
-       "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16",
-       "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16",
-       "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX",
-       "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>;
-
-  // 4.2.11 Sum of Absolute Difference
-  def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >;
-  def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>],
-        (instregex "USADA8")>;
-
-  // 4.2.12 Integer Multiply (32-bit result)
-  // Two sources.
-  def : InstRW< [SwiftWriteP0FourCycle],
-        (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
-        "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL",
-        "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT",
-        "t2SMULWB", "t2SMULWT", "t2SMUSD")>;
-
-  def SwiftWriteP0P01FiveCycleTwoUops :
-      SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]>  {
-    let Latency = 5;
-  }
-
-  def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[
-    SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>,
-    SchedVar<NoSchedPred,      [ SwiftWriteP0FourCycle ]>
-  ]>;
-
-  def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[
-     SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>,
-     SchedVar<NoSchedPred,      [ReadALU]>
-  ]>;
-
-  // Multiply accumulate, three sources
-  def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
-                 SwiftReadAdvanceFourCyclesPred],
-        (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
-        "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS",
-        "t2SMMLSR")>;
-
-  // 4.2.13 Integer Multiply (32-bit result, Q flag)
-  def : InstRW< [SwiftWriteP0FourCycle],
-        (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>;
-  def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
-                 SwiftReadAdvanceFourCyclesPred],
-        (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX",
-        "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT",
-        "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>;
-  def : InstRW< [SwiftPredP0P01FourFiveCycle],
-        (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>;
-
-  def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
-    let Latency = 5;
-    let NumMicroOps = 3;
-    let ResourceCycles = [2, 1];
-  }
-  def SwiftWrite1Cycle : SchedWriteRes<[]> {
-    let Latency = 1;
-    let NumMicroOps = 0;
-  }
-  def SwiftWrite5Cycle : SchedWriteRes<[]> {
-    let Latency = 5;
-    let NumMicroOps = 0;
-  }
-  def SwiftWrite6Cycle : SchedWriteRes<[]> {
-    let Latency = 6;
-    let NumMicroOps = 0;
-  }
-
-  // 4.2.14 Integer Multiply, Long
-  def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle],
-        (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
-
-  def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
-    let Latency = 7;
-    let NumMicroOps = 5;
-    let ResourceCycles = [2, 3];
-  }
-
-  // 4.2.15 Integer Multiply Accumulate, Long
-  // 4.2.16 Integer Multiply Accumulate, Dual
-  // 4.2.17 Integer Multiply Accumulate Accumulate, Long
-  // We are being a bit inaccurate here.
-  def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU,
-                 SchedReadAdvance<4>, SchedReadAdvance<3>],
-        (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
-        "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
-        "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT",
-        "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX",
-        "t2UMAAL")>;
-
-  def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
-    let NumMicroOps = 1;
-    let Latency = 14;
-    let ResourceCycles = [1, 14];
-  }
-  // 4.2.18 Integer Divide
-  def : WriteRes<WriteDiv, [SwiftUnitDiv]>; // Workaround.
-  def : InstRW < [],
-        (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
-
-  // 4.2.19 Integer Load Single Element
-  // 4.2.20 Integer Load Signextended
-  def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
-    let Latency = 3;
-  }
-  def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
-    let Latency = 4;
-  }
-  def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01,
-                                                   SwiftUnitP01]> {
-    let Latency = 4;
-  }
-  def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> {
-    let Latency = 3;
-  }
-  def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2,
-                                                    SwiftUnitP01]> {
-    let Latency = 3;
-  }
-  def SwiftWrBackOne : SchedWriteRes<[]> {
-    let Latency = 1;
-    let NumMicroOps = 0;
-  }
-  def SwiftWriteLdFour : SchedWriteRes<[]> {
-    let Latency = 4;
-    let NumMicroOps = 0;
-  }
-   // Not accurate.
-  def : InstRW<[SwiftWriteP2ThreeCycle],
-        (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
-        "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
-        "tLDR(r|i|spi|pci|pciASM)")>;
-  def : InstRW<[SwiftWriteP2ThreeCycle],
-        (instregex "LDRH$",  "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>;
-  def : InstRW<[SwiftWriteP2P01FourCyle],
-        (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
-        "t2LDRpci_pic", "tLDRS(B|H)")>;
-  def : InstRW<[SwiftWriteP2P01ThreeCycle,  SwiftWrBackOne],
-        (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
-        "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
-        "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
-  def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne],
-        (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
-        "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>;
-
-  // 4.2.21 Integer Dual Load
-  // Not accurate.
-  def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour],
-        (instregex "t2LDRDi8", "LDRD$")>;
-  def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne],
-        (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
-
-  // 4.2.22 Integer Load, Multiple
-  // NumReg = 1 .. 16
-  foreach Lat = 3-25 in {
-    def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
-      let Latency = Lat;
-    }
-    def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { let Latency = Lat; }
-  }
-  // Predicate.
-  foreach NumAddr = 1-16 in {
-    def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(MI) == "#NumAddr>;
-  }
-  def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; }
-  def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>;
-  def SwiftWriteLM : SchedWriteVariant<[
-    SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>,
-    SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy]>,
-    SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy]>,
-    SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy]>,
-    SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy]>,
-    SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy]>,
-    SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy]>,
-    SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy]>,
-    SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy]>,
-    SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy]>,
-    SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy]>,
-    SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM15Cy]>,
-    SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM15Cy, SwiftWriteLM16Cy]>,
-    SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM15Cy, SwiftWriteLM16Cy,
-                                SwiftWriteLM17Cy]>,
-    SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5Cy, SwiftWriteLM6Cy,
-                                SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM12Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM15Cy, SwiftWriteLM16Cy,
-                                SwiftWriteLM17Cy, SwiftWriteLM18Cy]>,
-    // Unknow number of registers, just use resources for two registers.
-    SchedVar<NoSchedPred,      [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
-                                SwiftWriteLM5CyNo, SwiftWriteLM6CyNo,
-                                SwiftWriteLM7CyNo, SwiftWriteLM8CyNo,
-                                SwiftWriteLM9CyNo, SwiftWriteLM10CyNo,
-                                SwiftWriteLM11CyNo, SwiftWriteLM12CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteLM15CyNo, SwiftWriteLM16CyNo,
-                                SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]>
-
-  ]> { let Variadic=1; }
-
-  def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB],
-        (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
-        "(t|sys)LDM(IA|DA|DB|IB)$")>;
-  def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM],
-        (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
-        "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
-  def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
-        (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>;
-  // 4.2.23 Integer Store, Single Element
-  def : InstRW<[SwiftWriteP2],
-        (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
-        "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
-
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2],
-        (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
-        "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
-        "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
-        "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
-
-  // 4.2.24 Integer Store, Dual
-  def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle],
-        (instregex "STRD$", "t2STRDi8")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2,
-                SwiftWriteP01OneCycle],
-        (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
-
-  // 4.2.25 Integer Store, Multiple
-  def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
-    let Latency = 0;
-  }
-  foreach NumAddr = 1-16 in {
-     def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>;
-  }
-  def SwiftWriteSTM : SchedWriteVariant<[
-    SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>,
-    SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>,
-    SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>,
-    SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>,
-    SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>,
-    SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>,
-    SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>,
-    SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>,
-    SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>,
-    SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>,
-    SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>,
-    SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>,
-    SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>,
-    SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>,
-    SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>,
-    // Unknow number of registers, just use resources for two registers.
-    SchedVar<NoSchedPred,      [SwiftWriteSTM2]>
-  ]>;
-  def : InstRW<[SwiftWriteSTM],
-        (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
-        (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
-        "PUSH", "tPUSH")>;
-
-  // 4.2.26 Branch
-  def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
-  def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
-  def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
-
-  // 4.2.27 Not issued
-  def : InstRW<[], (instregex "t2IT", "IT", "NOP")>;
-
-  // 4.2.28 Advanced SIMD, Integer, 2 cycle
-  def : InstRW<[SwiftWriteP0TwoCycle],
-        (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
-                   "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
-                   "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
-                   "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF",
-                   "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
-
-  def : InstRW<[SwiftWriteP1TwoCycle],
-        (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
-
-  // 4.2.29 Advanced SIMD, Integer, 4 cycle
-  // 4.2.30 Advanced SIMD, Integer with Accumulate
-  def : InstRW<[SwiftWriteP0FourCycle],
-        (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
-        "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
-        "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD",
-        "VQSUB")>;
-  def : InstRW<[SwiftWriteP1FourCycle],
-        (instregex "VRECPE", "VRSQRTE")>;
-
-  // 4.2.31 Advanced SIMD, Add and Shift with Narrow
-  def : InstRW<[SwiftWriteP0P1FourCycle],
-        (instregex "VADDHN", "VSUBHN", "VSHRN")>;
-  def : InstRW<[SwiftWriteP0P1SixCycle],
-        (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
-                   "VQRSHRN", "VQRSHRUN")>;
-
-  // 4.2.32 Advanced SIMD, Vector Table Lookup
-  foreach Num = 1-4 in {
-    def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>;
-  }
-  def : InstRW<[SwiftWrite1xP1TwoCycle],
-        (instregex "VTB(L|X)1")>;
-  def : InstRW<[SwiftWrite2xP1TwoCycle],
-        (instregex "VTB(L|X)2")>;
-  def : InstRW<[SwiftWrite3xP1TwoCycle],
-        (instregex "VTB(L|X)3")>;
-  def : InstRW<[SwiftWrite4xP1TwoCycle],
-        (instregex "VTB(L|X)4")>;
-
-  // 4.2.33 Advanced SIMD, Transpose
-  def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle,
-                SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>],
-        (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
-
-  // 4.2.34 Advanced SIMD and VFP, Floating Point
-  def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>;
-  def : InstRW<[SwiftWriteP0FourCycle],
-        (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>;
-  def : InstRW<[SwiftWriteP0FourCycle],
-        (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX",
-                   "VPMIN")>;
-  def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>;
-  def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>;
-
-  // 4.2.35 Advanced SIMD and VFP, Multiply
-  def : InstRW<[SwiftWriteP1FourCycle],
-        (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
-                   "VMULL", "VQDMULL")>;
-  def : InstRW<[SwiftWriteP1SixCycle],
-        (instregex "VMULD", "VNMULD")>;
-  def : InstRW<[SwiftWriteP1FourCycle],
-        (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)",
-        "VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>;
-  def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>;
-  def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>;
-
-  // 4.2.36 Advanced SIMD and VFP, Convert
-  def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
-  // Fixpoint conversions.
-  def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; }
-
-  // 4.2.37 Advanced SIMD and VFP, Move
-  def : InstRW<[SwiftWriteP0TwoCycle],
-        (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
-                   "VMVNv", "VMVN(d|q)", "VMVN(S|D)cc",
-                   "FCONST(D|S)")>;
-  def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
-        (instregex "VQMOVN")>;
-  def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
-        (instregex "VDUP(8|16|32)")>;
-  def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
-        (instregex "VMOVSR$", "VSETLN")>;
-  def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle],
-        (instregex "VMOVRR(D|S)$")>;
-  def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>,
-                WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle,
-                               SwiftWriteP1TwoCycle]>],
-                (instregex "VMOVSRR$")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>],
-        (instregex "VGETLN(u|i)")>;
-  def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle,
-                               SwiftWriteP01OneCycle]>],
-        (instregex "VGETLNs")>;
-
-  // 4.2.38 Advanced SIMD and VFP, Move FPSCR
-  // Serializing instructions.
-  def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
-    let Latency = 15;
-    let ResourceCycles = [15];
-  }
-  def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
-    let Latency = 15;
-    let ResourceCycles = [15];
-  }
-  def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
-    let Latency = 15;
-    let ResourceCycles = [15];
-  }
-  def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
-        (instregex "VMRS")>;
-  def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
-        (instregex "VMSR")>;
-  // Not serializing.
-  def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
-
-  // 4.2.39 Advanced SIMD and VFP, Load Single Element
-  def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
-
-  // 4.2.40 Advanced SIMD and VFP, Store Single Element
-  def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>;
-
-  // 4.2.41 Advanced SIMD and VFP, Load Multiple
-  // 4.2.42 Advanced SIMD and VFP, Store Multiple
-
-  // Resource requirement for permuting, just reserves the resources.
-  foreach Num = 1-28 in {
-    def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
-      let Latency = 0;
-      let NumMicroOps = Num;
-      let ResourceCycles = [Num];
-    }
-  }
-
-  // Pre RA pseudos - load/store to a Q register as a D register pair.
-  def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>;
-
-  // Post RA not modelled accurately. We assume that register use of width 64
-  // bit maps to a D register, 128 maps to a Q register. Not all different kinds
-  // are accurately represented.
-  def SwiftWriteVLDM : SchedWriteVariant<[
-    // Load of one S register.
-    SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>,
-    // Load of one D register.
-    SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>,
-    // Load of 3 S register.
-    SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm3]>,
-    // Load of a Q register (not neccessarily true). We should not be mapping to
-    // 4 S registers, either.
-    SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo,
-                                SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>,
-    // Load of 5 S registers.
-    SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteLM17CyNo,  SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm5]>,
-    // Load of 3 D registers. (Must also be able to handle s register list -
-    // though, not accurate)
-    SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM10Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
-    // Load of 7 S registers.
-    SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm7]>,
-    // Load of two Q registers.
-    SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteP01OneCycle,  SwiftVLDMPerm2]>,
-    // Load of 9 S registers.
-    SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm9]>,
-    // Load of 5 D registers.
-    SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM10Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
-                                SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
-    // Inaccurate: reuse describtion from 9 S registers.
-    SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm9]>,
-    // Load of three Q registers.
-    SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM11Cy,
-                                SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
-                                SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
-                                SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
-                                SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
-                                SwiftWriteP01OneCycle, SwiftVLDMPerm3]>,
-    // Inaccurate: reuse describtion from 9 S registers.
-    SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm9]>,
-    // Load of 7 D registers inaccurate.
-    SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM10Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM14Cy, SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
-                                SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
-                                SwiftWriteP01OneCycle, SwiftVLDMPerm7]>,
-    SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM17Cy, SwiftWriteLM18CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
-                                SwiftVLDMPerm9]>,
-    // Load of 4 Q registers.
-    SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy,
-                                SwiftWriteLM11Cy, SwiftWriteLM14Cy,
-                                SwiftWriteLM15Cy, SwiftWriteLM18CyNo,
-                                SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
-                                SwiftWriteP01OneCycle, SwiftVLDMPerm4]>,
-    // Unknow number of registers, just use resources for two registers.
-    SchedVar<NoSchedPred,      [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
-                                SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
-                                SwiftWriteP01OneCycle,  SwiftVLDMPerm2]>
-  ]> { let Variadic = 1; }
-
-  def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>;
-
-  def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM],
-        (instregex "VLDM[SD](IA|DB)_UPD$")>;
-
-  def SwiftWriteVSTM : SchedWriteVariant<[
-    // One S register.
-    SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>,
-    // One D register.
-    SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>,
-    // Three S registers.
-    SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>,
-    // Assume one Q register.
-    SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>,
-    SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>,
-    // Assume three D registers.
-    SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>,
-    SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>,
-    // Assume two Q registers.
-    SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>,
-    SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>,
-    // Assume 5 D registers.
-    SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>,
-    SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>,
-    // Asume three Q registers.
-    SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>,
-    SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>,
-    // Assume 7 D registers.
-    SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>,
-    SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>,
-    // Assume four Q registers.
-    SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>,
-    // Asumme two Q registers.
-    SchedVar<NoSchedPred, [SwiftWriteSTM3]>
-  ]> { let Variadic = 1; }
-
-  def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>;
-
-  def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM],
-        (instregex "VSTM[SD](IA|DB)_UPD")>;
-
-  // 4.2.43 Advanced SIMD, Element or Structure Load and Store
-  def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
-      let Latency = 4;
-      let ResourceCycles = [2];
-  }
-  def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
-      let Latency = 4;
-      let ResourceCycles = [3];
-  }
-  foreach Num = 1-2 in {
-    def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
-      let Latency = 0;
-      let NumMicroOps = Num;
-      let ResourceCycles = [Num];
-    }
-  }
-  // VLDx
-  // Multiple structures.
-  // Single element structure loads.
-  // We assume aligned.
-  // Single/two register.
-  def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>;
-  def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle],
-        (instregex "VLD1(d|q)(8|16|32|64)wb")>;
-  // Three register.
-  def : InstRW<[SwiftWrite3xP2FourCy],
-        (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>;
-  def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle],
-        (instregex "VLD1(d|q)(8|16|32|64)Twb")>;
-  /// Four Register.
-  def : InstRW<[SwiftWrite2xP2FourCy],
-        (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>;
-  def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle],
-        (instregex "VLD1(d|q)(8|16|32|64)Qwb")>;
-  // Two element structure loads.
-  // Two/four register.
-  def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2],
-        (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
-                SwiftVLDMPerm2],
-        (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>;
-  // Three element structure.
-  def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
-                SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
-        (instregex "VLD3(d|q)(8|16|32)$")>;
-  def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
-        (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>;
-
-  def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
-                SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
-        (instregex "VLD3(d|q)(8|16|32)_UPD$")>;
-  def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3,
-                SwiftWrite3xP2FourCy],
-        (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
-  // Four element structure loads.
-  def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
-                SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
-                SwiftWrite3xP2FourCy],
-        (instregex "VLD4(d|q)(8|16|32)$")>;
-  def : InstRW<[SwiftWriteLM11Cy,  SwiftExt2xP0, SwiftVLDMPerm4,
-                SwiftWrite3xP2FourCy],
-        (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>;
-  def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
-                SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
-                SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
-        (instregex "VLD4(d|q)(8|16|32)_UPD")>;
-  def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
-                SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
-        (instregex  "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
-
-  // Single all/lane loads.
-  // One element structure.
-  def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2],
-        (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2],
-        (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)",
-                  "VLD1LNq(8|16|32)Pseudo_UPD")>;
-  // Two element structure.
-  def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2],
-        (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
-                   "VLD2LN(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle,
-                SwiftExt1xP0, SwiftVLDMPerm2],
-        (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>;
-  def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
-                SwiftExt1xP0, SwiftVLDMPerm2],
-        (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>;
-  def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
-                SwiftExt1xP0, SwiftVLDMPerm2],
-        (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>;
-  // Three element structure.
-  def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0,
-                SwiftVLDMPerm3],
-        (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$",
-                   "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy,
-                SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3],
-        (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>;
-  def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy,
-                SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3],
-        (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>;
-  // Four element struture.
-  def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
-                SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5],
-        (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$",
-                   "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
-                SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0,
-                SwiftVLDMPerm5],
-        (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>;
-  def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy,
-                SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0,
-                SwiftVLDMPerm5],
-        (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>;
-  // VSTx
-  // Multiple structures.
-  // Single element structure store.
-  def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>;
-  def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2],
-        (instregex "VST1d(8|16|32|64)wb")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2],
-        (instregex "VST1q(8|16|32|64)wb")>;
-  def : InstRW<[SwiftWrite3xP2],
-        (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2],
-        (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>;
-  def : InstRW<[SwiftWrite4xP2],
-        (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2],
-        (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>;
-  // Two element structure store.
-  def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
-        (instregex "VST2(d|b)(8|16|32)$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
-        (instregex "VST2(b|d)(8|16|32)wb")>;
-  def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
-        (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
-        (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>;
-  // Three element structure store.
-  def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
-        (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
-        (instregex "VST3(d|q)(8|16|32)_UPD",
-                   "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
-  // Four element structure store.
-  def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
-        (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4],
-        (instregex "VST4(d|q)(8|16|32)_UPD",
-                   "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
-  // Single/all lane store.
-  // One element structure.
-  def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
-        (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
-        (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>;
-  // Two element structure.
-  def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2],
-        (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2],
-        (instregex "VST2LN(d|q)(8|16|32)_UPD",
-                   "VST2LN(d|q)(8|16|32)Pseudo_UPD")>;
-  // Three element structure.
-  def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
-        (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
-        (instregex "VST3LN(d|q)(8|16|32)_UPD",
-                   "VST3LN(d|q)(8|16|32)Pseudo_UPD")>;
-  // Four element structure.
-  def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
-        (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>;
-  def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2],
-        (instregex "VST4LN(d|q)(8|16|32)_UPD",
-                   "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
-
-  // 4.2.44 VFP, Divide and Square Root
-  def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
-    let NumMicroOps = 1;
-    let Latency = 17;
-    let ResourceCycles = [1, 15];
-  }
-  def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
-    let NumMicroOps = 1;
-    let Latency = 32;
-    let ResourceCycles = [1, 30];
-  }
-  def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
-  def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
-
-  // Not specified.
-  def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
-  // Preload.
-  def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
-    let ResourceCycles = [0];
-  }
-
+  def : WriteRes<WriteCMPsi, [SwiftUnitP01]>;
+  def : WriteRes<WriteCMPsr, [SwiftUnitP01]>;
 }

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=183273&r1=183272&r2=183273&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Jun  4 17:35:17 2013
@@ -1340,11 +1340,11 @@ void SubtargetEmitter::EmitSchedModelHel
         for (std::vector<CodeGenSchedTransition>::const_iterator
                TI = SC.Transitions.begin(), TE = SC.Transitions.end();
              TI != TE; ++TI) {
+          OS << "      if (";
           if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
                                       TI->ProcIndices.end(), *PI)) {
               continue;
           }
-          OS << "      if (";
           for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
                RI != RE; ++RI) {
             if (RI != TI->PredTerm.begin())





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