[PATCH 2/2] R600: Use new getNamedOperandIdx function generated by TableGen.
Tom Stellard
tom at stellard.net
Mon Jun 3 14:23:23 PDT 2013
From: Tom Stellard <thomas.stellard at amd.com>
---
lib/Target/R600/AMDGPUInstrInfo.cpp | 1 +
lib/Target/R600/AMDGPUInstrInfo.h | 5 +
lib/Target/R600/AMDILISelDAGToDAG.cpp | 27 ++---
lib/Target/R600/R600Defines.h | 41 +-------
lib/Target/R600/R600ExpandSpecialInstrs.cpp | 16 +--
lib/Target/R600/R600ISelLowering.cpp | 2 +-
lib/Target/R600/R600InstrInfo.cpp | 156 +++++++++++-----------------
lib/Target/R600/R600InstrInfo.h | 6 +-
lib/Target/R600/R600Packetizer.cpp | 18 ++--
9 files changed, 103 insertions(+), 169 deletions(-)
diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp
index 45d886d..51805b3 100644
--- a/lib/Target/R600/AMDGPUInstrInfo.cpp
+++ b/lib/Target/R600/AMDGPUInstrInfo.cpp
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRMAP_INFO
#include "AMDGPUGenInstrInfo.inc"
diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h
index 3909e4e..152105f 100644
--- a/lib/Target/R600/AMDGPUInstrInfo.h
+++ b/lib/Target/R600/AMDGPUInstrInfo.h
@@ -23,6 +23,7 @@
#define GET_INSTRINFO_HEADER
#define GET_INSTRINFO_ENUM
+#define GET_INSTRINFO_OPERAND_ENUM
#include "AMDGPUGenInstrInfo.inc"
#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
@@ -198,6 +199,10 @@ public:
};
+namespace AMDGPU {
+ int getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
+} // End namespace AMDGPU
+
} // End llvm namespace
#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp
index 00d7c8f..8364517 100644
--- a/lib/Target/R600/AMDILISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp
@@ -278,7 +278,8 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
continue;
}
- int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
+ int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(),
+ AMDGPU::OpName::LITERAL);
assert(ImmIdx != -1);
// subtract one from ImmIdx, because the DST operand is usually index
@@ -341,7 +342,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
if (PotentialClamp->isMachineOpcode() &&
PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
unsigned ClampIdx =
- TII->getOperandIdx(Result->getMachineOpcode(), R600Operands::CLAMP);
+ TII->getOperandIdx(Result->getMachineOpcode(), AMDGPU::OpName::CLAMP);
std::vector<SDValue> Ops;
unsigned NumOp = Result->getNumOperands();
for (unsigned i = 0; i < NumOp; ++i) {
@@ -362,23 +363,23 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
int OperandIdx[] = {
- TII->getOperandIdx(Opcode, R600Operands::SRC0),
- TII->getOperandIdx(Opcode, R600Operands::SRC1),
- TII->getOperandIdx(Opcode, R600Operands::SRC2)
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC0),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC1),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC2)
};
int SelIdx[] = {
- TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
- TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
- TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC0_SEL),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC1_SEL),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC2_SEL)
};
int NegIdx[] = {
- TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
- TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
- TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC0_NEG),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC1_NEG),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC2_NEG)
};
int AbsIdx[] = {
- TII->getOperandIdx(Opcode, R600Operands::SRC0_ABS),
- TII->getOperandIdx(Opcode, R600Operands::SRC1_ABS),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC0_ABS),
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC1_ABS),
-1
};
diff --git a/lib/Target/R600/R600Defines.h b/lib/Target/R600/R600Defines.h
index aebe581..e30ea27 100644
--- a/lib/Target/R600/R600Defines.h
+++ b/lib/Target/R600/R600Defines.h
@@ -57,46 +57,7 @@ namespace R600_InstFlag {
#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
-namespace R600Operands {
- enum Ops {
- DST,
- UPDATE_EXEC_MASK,
- UPDATE_PREDICATE,
- WRITE,
- OMOD,
- DST_REL,
- CLAMP,
- SRC0,
- SRC0_NEG,
- SRC0_REL,
- SRC0_ABS,
- SRC0_SEL,
- SRC1,
- SRC1_NEG,
- SRC1_REL,
- SRC1_ABS,
- SRC1_SEL,
- SRC2,
- SRC2_NEG,
- SRC2_REL,
- SRC2_SEL,
- LAST,
- PRED_SEL,
- IMM,
- BANK_SWIZZLE,
- COUNT
- };
-
- const static int ALUOpTable[3][R600Operands::COUNT] = {
-// W C S S S S S S S S S S S
-// R O D L S R R R R S R R R R S R R R L P
-// D U I M R A R C C C C R C C C C R C C C A R I
-// S E U T O E M C 0 0 0 0 C 1 1 1 1 C 2 2 2 S E M B
-// T M P E D L P 0 N R A S 1 N R A S 2 N R S T D M S
- {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12,13},
- {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19,20},
- {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17,18}
- };
+namespace OpName {
enum VecOps {
UPDATE_EXEC_MASK_X,
diff --git a/lib/Target/R600/R600ExpandSpecialInstrs.cpp b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
index b9d5303..1ed8969 100644
--- a/lib/Target/R600/R600ExpandSpecialInstrs.cpp
+++ b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
@@ -81,9 +81,9 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
AMDGPU::ZERO); // src1
TII->addFlag(PredSet, 0, MO_FLAG_MASK);
if (Flags & MO_FLAG_PUSH) {
- TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
+ TII->setImmOperand(PredSet, AMDGPU::OpName::UPDATE_EXEC_MASK, 1);
} else {
- TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1);
+ TII->setImmOperand(PredSet, AMDGPU::OpName::UPDATE_PRED, 1);
}
MI.eraseFromParent();
continue;
@@ -95,7 +95,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
AMDGPU::ZERO,
AMDGPU::ZERO);
TII->addFlag(PredSet, 0, MO_FLAG_MASK);
- TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
+ TII->setImmOperand(PredSet, AMDGPU::OpName::UPDATE_EXEC_MASK, 1);
BuildMI(MBB, I, MBB.findDebugLoc(I),
TII->get(AMDGPU::PREDICATED_BREAK))
@@ -207,10 +207,10 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
// While not strictly necessary from hw point of view, we force
// all src operands of a dot4 inst to belong to the same slot.
unsigned Src0 = BMI->getOperand(
- TII->getOperandIdx(Opcode, R600Operands::SRC0))
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC0))
.getReg();
unsigned Src1 = BMI->getOperand(
- TII->getOperandIdx(Opcode, R600Operands::SRC1))
+ TII->getOperandIdx(Opcode, AMDGPU::OpName::SRC1))
.getReg();
(void) Src0;
(void) Src1;
@@ -255,14 +255,14 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
// T0_W = CUBE T1_Y, T1_Z
for (unsigned Chan = 0; Chan < 4; Chan++) {
unsigned DstReg = MI.getOperand(
- TII->getOperandIdx(MI, R600Operands::DST)).getReg();
+ TII->getOperandIdx(MI, AMDGPU::OpName::DST)).getReg();
unsigned Src0 = MI.getOperand(
- TII->getOperandIdx(MI, R600Operands::SRC0)).getReg();
+ TII->getOperandIdx(MI, AMDGPU::OpName::SRC0)).getReg();
unsigned Src1 = 0;
// Determine the correct source registers
if (!IsCube) {
- int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1);
+ int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::SRC1);
if (Src1Idx != -1) {
Src1 = MI.getOperand(Src1Idx).getReg();
}
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index de6c504..60a1441 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -167,7 +167,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::CONST_COPY: {
MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
- TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
+ TII->setImmOperand(NewMI, AMDGPU::OpName::SRC0_SEL,
MI->getOperand(1).getImm());
break;
}
diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp
index 5f8486d..42e62a4 100644
--- a/lib/Target/R600/R600InstrInfo.cpp
+++ b/lib/Target/R600/R600InstrInfo.cpp
@@ -69,7 +69,7 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
DestReg, SrcReg);
- NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
+ NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::SRC0))
.setIsKill(KillSrc);
}
}
@@ -169,10 +169,10 @@ SmallVector<std::pair<MachineOperand *, int64_t>, 3>
R600InstrInfo::getSrcs(MachineInstr *MI) const {
SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
- static const R600Operands::Ops OpTable[3][2] = {
- {R600Operands::SRC0, R600Operands::SRC0_SEL},
- {R600Operands::SRC1, R600Operands::SRC1_SEL},
- {R600Operands::SRC2, R600Operands::SRC2_SEL},
+ static const unsigned OpTable[3][2] = {
+ {AMDGPU::OpName::SRC0, AMDGPU::OpName::SRC0_SEL},
+ {AMDGPU::OpName::SRC1, AMDGPU::OpName::SRC1_SEL},
+ {AMDGPU::OpName::SRC2, AMDGPU::OpName::SRC2_SEL},
};
for (unsigned j = 0; j < 3; j++) {
@@ -189,7 +189,7 @@ R600InstrInfo::getSrcs(MachineInstr *MI) const {
}
if (Reg == AMDGPU::ALU_LITERAL_X) {
unsigned Imm = MI->getOperand(
- getOperandIdx(MI->getOpcode(), R600Operands::IMM)).getImm();
+ getOperandIdx(MI->getOpcode(), AMDGPU::OpName::LITERAL)).getImm();
Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
continue;
}
@@ -304,7 +304,7 @@ R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
for (unsigned i = 0, e = IG.size(); i < e; ++i) {
IGSrcs.push_back(ExtractSrcs(IG[i], PV));
unsigned Op = getOperandIdx(IG[i]->getOpcode(),
- R600Operands::BANK_SWIZZLE);
+ AMDGPU::OpName::BANK_SWIZZLE);
ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
IG[i]->getOperand(Op).getImm());
}
@@ -787,12 +787,12 @@ MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
AMDGPU::AR_X, OffsetReg);
- setImmOperand(MOVA, R600Operands::WRITE, 0);
+ setImmOperand(MOVA, AMDGPU::OpName::WRITE, 0);
MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
AddrReg, ValueReg)
.addReg(AMDGPU::AR_X, RegState::Implicit);
- setImmOperand(Mov, R600Operands::DST_REL, 1);
+ setImmOperand(Mov, AMDGPU::OpName::DST_REL, 1);
return Mov;
}
@@ -804,12 +804,12 @@ MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
AMDGPU::AR_X,
OffsetReg);
- setImmOperand(MOVA, R600Operands::WRITE, 0);
+ setImmOperand(MOVA, AMDGPU::OpName::WRITE, 0);
MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
ValueReg,
AddrReg)
.addReg(AMDGPU::AR_X, RegState::Implicit);
- setImmOperand(Mov, R600Operands::SRC0_REL, 1);
+ setImmOperand(Mov, AMDGPU::OpName::SRC0_REL, 1);
return Mov;
}
@@ -865,7 +865,7 @@ MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MB
#define OPERAND_CASE(Label) \
case Label: { \
- static const R600Operands::VecOps Ops[] = \
+ static const unsigned Ops[] = \
{ \
Label##_X, \
Label##_Y, \
@@ -875,26 +875,25 @@ MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MB
return Ops[Slot]; \
}
-static R600Operands::VecOps
-getSlotedOps(R600Operands::Ops Op, unsigned Slot) {
+static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
switch (Op) {
- OPERAND_CASE(R600Operands::UPDATE_EXEC_MASK)
- OPERAND_CASE(R600Operands::UPDATE_PREDICATE)
- OPERAND_CASE(R600Operands::WRITE)
- OPERAND_CASE(R600Operands::OMOD)
- OPERAND_CASE(R600Operands::DST_REL)
- OPERAND_CASE(R600Operands::CLAMP)
- OPERAND_CASE(R600Operands::SRC0)
- OPERAND_CASE(R600Operands::SRC0_NEG)
- OPERAND_CASE(R600Operands::SRC0_REL)
- OPERAND_CASE(R600Operands::SRC0_ABS)
- OPERAND_CASE(R600Operands::SRC0_SEL)
- OPERAND_CASE(R600Operands::SRC1)
- OPERAND_CASE(R600Operands::SRC1_NEG)
- OPERAND_CASE(R600Operands::SRC1_REL)
- OPERAND_CASE(R600Operands::SRC1_ABS)
- OPERAND_CASE(R600Operands::SRC1_SEL)
- OPERAND_CASE(R600Operands::PRED_SEL)
+ OPERAND_CASE(AMDGPU::OpName::UPDATE_EXEC_MASK)
+ OPERAND_CASE(AMDGPU::OpName::UPDATE_PRED)
+ OPERAND_CASE(AMDGPU::OpName::WRITE)
+ OPERAND_CASE(AMDGPU::OpName::OMOD)
+ OPERAND_CASE(AMDGPU::OpName::DST_REL)
+ OPERAND_CASE(AMDGPU::OpName::CLAMP)
+ OPERAND_CASE(AMDGPU::OpName::SRC0)
+ OPERAND_CASE(AMDGPU::OpName::SRC0_NEG)
+ OPERAND_CASE(AMDGPU::OpName::SRC0_REL)
+ OPERAND_CASE(AMDGPU::OpName::SRC0_ABS)
+ OPERAND_CASE(AMDGPU::OpName::SRC0_SEL)
+ OPERAND_CASE(AMDGPU::OpName::SRC1)
+ OPERAND_CASE(AMDGPU::OpName::SRC1_NEG)
+ OPERAND_CASE(AMDGPU::OpName::SRC1_REL)
+ OPERAND_CASE(AMDGPU::OpName::SRC1_ABS)
+ OPERAND_CASE(AMDGPU::OpName::SRC1_SEL)
+ OPERAND_CASE(AMDGPU::OpName::PRED_SEL)
default:
llvm_unreachable("Wrong Operand");
}
@@ -902,12 +901,6 @@ getSlotedOps(R600Operands::Ops Op, unsigned Slot) {
#undef OPERAND_CASE
-static int
-getVecOperandIdx(R600Operands::VecOps Op) {
- return 1 + Op;
-}
-
-
MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
const {
@@ -920,31 +913,31 @@ MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
Opcode = AMDGPU::DOT4_eg;
MachineBasicBlock::iterator I = MI;
MachineOperand &Src0 = MI->getOperand(
- getVecOperandIdx(getSlotedOps(R600Operands::SRC0, Slot)));
+ getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::SRC0, Slot)));
MachineOperand &Src1 = MI->getOperand(
- getVecOperandIdx(getSlotedOps(R600Operands::SRC1, Slot)));
+ getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::SRC1, Slot)));
MachineInstr *MIB = buildDefaultInstruction(
MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
- static const R600Operands::Ops Operands[14] = {
- R600Operands::UPDATE_EXEC_MASK,
- R600Operands::UPDATE_PREDICATE,
- R600Operands::WRITE,
- R600Operands::OMOD,
- R600Operands::DST_REL,
- R600Operands::CLAMP,
- R600Operands::SRC0_NEG,
- R600Operands::SRC0_REL,
- R600Operands::SRC0_ABS,
- R600Operands::SRC0_SEL,
- R600Operands::SRC1_NEG,
- R600Operands::SRC1_REL,
- R600Operands::SRC1_ABS,
- R600Operands::SRC1_SEL,
+ static const unsigned Operands[14] = {
+ AMDGPU::OpName::UPDATE_EXEC_MASK,
+ AMDGPU::OpName::UPDATE_PRED,
+ AMDGPU::OpName::WRITE,
+ AMDGPU::OpName::OMOD,
+ AMDGPU::OpName::DST_REL,
+ AMDGPU::OpName::CLAMP,
+ AMDGPU::OpName::SRC0_NEG,
+ AMDGPU::OpName::SRC0_REL,
+ AMDGPU::OpName::SRC0_ABS,
+ AMDGPU::OpName::SRC0_SEL,
+ AMDGPU::OpName::SRC1_NEG,
+ AMDGPU::OpName::SRC1_REL,
+ AMDGPU::OpName::SRC1_ABS,
+ AMDGPU::OpName::SRC1_SEL,
};
for (unsigned i = 0; i < 14; i++) {
MachineOperand &MO = MI->getOperand(
- getVecOperandIdx(getSlotedOps(Operands[i], Slot)));
+ getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
assert (MO.isImm());
setImmOperand(MIB, Operands[i], MO.getImm());
}
@@ -958,46 +951,19 @@ MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
uint64_t Imm) const {
MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
AMDGPU::ALU_LITERAL_X);
- setImmOperand(MovImm, R600Operands::IMM, Imm);
+ setImmOperand(MovImm, AMDGPU::OpName::LITERAL, Imm);
return MovImm;
}
-int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
- R600Operands::Ops Op) const {
+int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
return getOperandIdx(MI.getOpcode(), Op);
}
-int R600InstrInfo::getOperandIdx(unsigned Opcode,
- R600Operands::Ops Op) const {
- unsigned TargetFlags = get(Opcode).TSFlags;
- unsigned OpTableIdx;
-
- if (!HAS_NATIVE_OPERANDS(TargetFlags)) {
- switch (Op) {
- case R600Operands::DST: return 0;
- case R600Operands::SRC0: return 1;
- case R600Operands::SRC1: return 2;
- case R600Operands::SRC2: return 3;
- default:
- assert(!"Unknown operand type for instruction");
- return -1;
- }
- }
-
- if (TargetFlags & R600_InstFlag::OP1) {
- OpTableIdx = 0;
- } else if (TargetFlags & R600_InstFlag::OP2) {
- OpTableIdx = 1;
- } else {
- assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
- "for this instruction");
- OpTableIdx = 2;
- }
-
- return R600Operands::ALUOpTable[OpTableIdx][Op];
+int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
+ return AMDGPU::getNamedOperandIdx(Opcode, Op);
}
-void R600InstrInfo::setImmOperand(MachineInstr *MI, R600Operands::Ops Op,
+void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
int64_t Imm) const {
int Idx = getOperandIdx(*MI, Op);
assert(Idx != -1 && "Operand not supported for this instruction.");
@@ -1025,20 +991,20 @@ MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
switch (Flag) {
case MO_FLAG_CLAMP:
- FlagIndex = getOperandIdx(*MI, R600Operands::CLAMP);
+ FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::CLAMP);
break;
case MO_FLAG_MASK:
- FlagIndex = getOperandIdx(*MI, R600Operands::WRITE);
+ FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::WRITE);
break;
case MO_FLAG_NOT_LAST:
case MO_FLAG_LAST:
- FlagIndex = getOperandIdx(*MI, R600Operands::LAST);
+ FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::LAST);
break;
case MO_FLAG_NEG:
switch (SrcIdx) {
- case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_NEG); break;
- case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_NEG); break;
- case 2: FlagIndex = getOperandIdx(*MI, R600Operands::SRC2_NEG); break;
+ case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::SRC0_NEG); break;
+ case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::SRC1_NEG); break;
+ case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::SRC2_NEG); break;
}
break;
@@ -1047,8 +1013,8 @@ MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
"instructions.");
(void)IsOP3;
switch (SrcIdx) {
- case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_ABS); break;
- case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_ABS); break;
+ case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::SRC0_ABS); break;
+ case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::SRC1_ABS); break;
}
break;
diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h
index f9ccf4f..0498ae8 100644
--- a/lib/Target/R600/R600InstrInfo.h
+++ b/lib/Target/R600/R600InstrInfo.h
@@ -211,15 +211,15 @@ namespace llvm {
/// \brief Get the index of Op in the MachineInstr.
///
/// \returns -1 if the Instruction does not contain the specified \p Op.
- int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
+ int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
/// \brief Get the index of \p Op for the given Opcode.
///
/// \returns -1 if the Instruction does not contain the specified \p Op.
- int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
+ int getOperandIdx(unsigned Opcode, unsigned Op) const;
/// \brief Helper function for setting instruction flag values.
- void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
+ void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
/// \returns true if this instruction has an operand for storing target flags.
bool hasFlagOperand(const MachineInstr &MI) const;
diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp
index 033c0b4..12bb0d2 100644
--- a/lib/Target/R600/R600Packetizer.cpp
+++ b/lib/Target/R600/R600Packetizer.cpp
@@ -79,7 +79,7 @@ private:
continue;
if (TII->isTransOnly(BI))
continue;
- int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
+ int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::WRITE);
if (OperandIdx < 0)
continue;
if (BI->getOperand(OperandIdx).getImm() == 0)
@@ -114,10 +114,10 @@ private:
void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
const {
- R600Operands::Ops Ops[] = {
- R600Operands::SRC0,
- R600Operands::SRC1,
- R600Operands::SRC2
+ unsigned Ops[] = {
+ AMDGPU::OpName::SRC0,
+ AMDGPU::OpName::SRC1,
+ AMDGPU::OpName::SRC2
};
for (unsigned i = 0; i < 3; i++) {
int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
@@ -166,8 +166,8 @@ public:
if (getSlot(MII) <= getSlot(MIJ))
return false;
// Does MII and MIJ share the same pred_sel ?
- int OpI = TII->getOperandIdx(MII->getOpcode(), R600Operands::PRED_SEL),
- OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600Operands::PRED_SEL);
+ int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::PRED_SEL),
+ OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::PRED_SEL);
unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
if (PredI != PredJ)
@@ -193,7 +193,7 @@ public:
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
- unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600Operands::LAST);
+ unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::LAST);
MI->getOperand(LastOp).setImm(Bit);
}
@@ -232,7 +232,7 @@ public:
for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
MachineInstr *MI = CurrentPacketMIs[i];
unsigned Op = TII->getOperandIdx(MI->getOpcode(),
- R600Operands::BANK_SWIZZLE);
+ AMDGPU::OpName::BANK_SWIZZLE);
MI->getOperand(Op).setImm(BS[i]);
}
}
--
1.7.11.4
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