[llvm] r183106 - R600: Constraints input regs of interp_xy,_zw
Rafael Ávila De Espíndola
rafael.espindola at gmail.com
Mon Jun 3 11:05:36 PDT 2013
Test case ?
Sent from my iPhone
On 2013-06-03, at 11:44, Vincent Lejeune <vljn at ovi.com> wrote:
> Author: vljn
> Date: Mon Jun 3 10:44:16 2013
> New Revision: 183106
>
> URL: http://llvm.org/viewvc/llvm-project?rev=183106&view=rev
> Log:
> R600: Constraints input regs of interp_xy,_zw
>
> Modified:
> llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> llvm/trunk/lib/Target/R600/R600Instructions.td
>
> Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=183106&r1=183105&r2=183106&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Mon Jun 3 10:44:16 2013
> @@ -543,21 +543,25 @@ SDValue R600TargetLowering::LowerOperati
> DL, MVT::f32, SDValue(interp, 0));
> }
>
> + MachineFunction &MF = DAG.getMachineFunction();
> + MachineRegisterInfo &MRI = MF.getRegInfo();
> + unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
> + unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
> + MRI.addLiveIn(RegisterI);
> + MRI.addLiveIn(RegisterJ);
> + SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
> + SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
> + SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
> + SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
> +
> if (slot % 4 < 2)
> interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
> MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
> - CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> - AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
> - CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> - AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
> + RegisterJNode, RegisterINode);
> else
> interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
> MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
> - CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> - AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
> - CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> - AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
> -
> + RegisterJNode, RegisterINode);
> return SDValue(interp, slot % 2);
> }
> case AMDGPUIntrinsic::R600_tex:
>
> Modified: llvm/trunk/lib/Target/R600/R600Instructions.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td?rev=183106&r1=183105&r2=183106&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600Instructions.td (original)
> +++ llvm/trunk/lib/Target/R600/R600Instructions.td Mon Jun 3 10:44:16 2013
> @@ -578,13 +578,13 @@ def isR600toCayman : Predicate<
>
> def INTERP_PAIR_XY : AMDGPUShaderInst <
> (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
> - (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
> + (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
> "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
> []>;
>
> def INTERP_PAIR_ZW : AMDGPUShaderInst <
> (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
> - (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
> + (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
> "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
> []>;
>
>
>
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