[llvm] r183134 - R600/SI: Handle REG_SEQUENCE in fitsRegClass()

[Tom Stellard]

Author: tstellar
Date: Mon Jun  3 12:39:54 2013
New Revision: 183134

URL: http://llvm.org/viewvc/llvm-project?rev=183134&view=rev
Log:
R600/SI: Handle REG_SEQUENCE in fitsRegClass()

Modified:
    llvm/trunk/lib/Target/R600/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=183134&r1=183133&r2=183134&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Mon Jun  3 12:39:54 2013
@@ -523,10 +523,20 @@ bool SITargetLowering::fitsRegClass(Sele
   if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
     const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
     int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
-    if (OpClassID == -1)
-      OpClass = getRegClassFor(Op.getSimpleValueType());
-    else
+    if (OpClassID == -1) {
+      switch (MN->getMachineOpcode()) {
+      case AMDGPU::REG_SEQUENCE:
+        // Operand 0 is the register class id for REG_SEQUENCE instructions.
+        OpClass = TRI->getRegClass(
+                       cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue());
+        break;
+      default:
+        OpClass = getRegClassFor(Op.getSimpleValueType());
+        break;
+      }
+    } else {
       OpClass = TRI->getRegClass(OpClassID);
+    }
 
   } else if (Node->getOpcode() == ISD::CopyFromReg) {
     RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());