[llvm] r183111 - R600: 3 op instructions have no write bit but the result are store in PV

[Vincent Lejeune]

Author: vljn
Date: Mon Jun  3 10:56:12 2013
New Revision: 183111

URL: http://llvm.org/viewvc/llvm-project?rev=183111&view=rev
Log:
R600: 3 op instructions have no write bit but the result are store in PV

Modified:
    llvm/trunk/lib/Target/R600/R600Packetizer.cpp

Modified: llvm/trunk/lib/Target/R600/R600Packetizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Packetizer.cpp?rev=183111&r1=183110&r2=183111&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600Packetizer.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600Packetizer.cpp Mon Jun  3 10:56:12 2013
@@ -80,9 +80,7 @@ private:
       if (TII->isTransOnly(BI))
         continue;
       int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600Operands::WRITE);
-      if (OperandIdx < 0)
-        continue;
-      if (BI->getOperand(OperandIdx).getImm() == 0)
+      if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
         continue;
       unsigned Dst = BI->getOperand(0).getReg();
       if (BI->getOpcode() == AMDGPU::DOT4_r600 ||