[PATCH, RFC] Recognize ValueType operands in source patterns for fast-isel

[Bill Schmidt]

It has been suggested that it might be appropriate to attach the patch.
Oops.  Please see below.

Thanks,
Bill

On Wed, 2013-05-22 at 14:39 -0500, Bill Schmidt wrote:
> Recognize ValueType operands in source patterns for fast-isel.
> 
> Currently the fast-isel table generator recognizes registers, register
> classes, and immediates for source pattern operands.  ValueType
> operands are not recognized.  This is not a problem for existing
> targets with fast-isel support, but will not work for targets like
> PowerPC and SPARC that use types in source patterns.
> 
> The proposed patch allows ValueType operands and treats them in the
> same manner as register classes.  There is no convenient way to map
> from a ValueType to a register class, but there's no need to do so.
> The table generator already requires that all types in the source
> pattern be identical, and we know the register class of the output
> operand already.  So we just assign that register class to any
> ValueType operands we encounter.
> 
> Does this look OK to apply?
> 
> Thanks,
> Bill
> 

Index: utils/TableGen/FastISelEmitter.cpp
===================================================================
--- utils/TableGen/FastISelEmitter.cpp	(revision 182420)
+++ utils/TableGen/FastISelEmitter.cpp	(working copy)
@@ -173,7 +173,8 @@ struct OperandsSignature {
   ///
   bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget
&Target,
                   MVT::SimpleValueType VT,
-                  ImmPredicateSet &ImmediatePredicates) {
+                  ImmPredicateSet &ImmediatePredicates,
+                  const CodeGenRegisterClass *OrigDstRC) {
     if (InstPatNode->isLeaf())
       return false;
     
@@ -258,7 +259,9 @@ struct OperandsSignature {
         RC = &Target.getRegisterClass(OpLeafRec);
       else if (OpLeafRec->isSubClassOf("Register"))
         RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
-      else
+      else if (OpLeafRec->isSubClassOf("ValueType")) {
+        RC = OrigDstRC;
+      } else
         return false;
 
       // For now, this needs to be a register class of some sort.
@@ -503,7 +506,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatter
 
     // Check all the operands.
     OperandsSignature Operands;
-    if (!Operands.initialize(InstPatNode, Target, VT,
ImmediatePredicates))
+    if (!Operands.initialize(InstPatNode, Target, VT,
ImmediatePredicates,
+                             DstRC))
       continue;
 
     std::vector<std::string>* PhysRegInputs = new
std::vector<std::string>();