[PATCH] Fix ARM encoding constraints for Q register fields and VSTn instructions

[Tim Northover]

Hi Mihail,

Although these are both changes to "fix VSTn disassembly", I think
they should probably be committed separately.

Both code changes look reasonable to me, but the test
invalid-VST2b32_UPD-arm.txt is semantically incorrect. The
disassembler will try to resynchronise the stream after the first
failure, but it will only skip 1 byte. So the file given won't
actually test what you think it does. The output of the llvm-mc
command is:
<stdin>:11:1: warning: invalid instruction encoding
0xb3 0x09 0x03 0xf4
^
<stdin>:11:6: warning: invalid instruction encoding
0xb3 0x09 0x03 0xf4
     ^
        stmeq   r3, {r0, r1, r10, r12, sp, lr, pc} ^
        ldmeq   r3!, {r0, r1, r10, r12, sp, lr, pc}
<stdin>:19:11: warning: invalid instruction encoding
0xb3 0x08 0x03 0xf4
          ^
<stdin>:19:16: warning: invalid instruction encoding
0xb3 0x08 0x03 0xf4
               ^

where those stmeq and ldmeq instructions come from disassembling
unintended sequences of bytes and the failures aren't for what you
think they should be.

Tim.