[PATCH] Fix ARM encoding constraints for Q register fields and VSTn instructions

[Mihail Popa]

Hello.

Kindly review the attached patch. It fixes two ARM disassembler issues:

1. Q registers are encoded in fields of the same length as D registers. 
As Q registers are half as many, the ARM reference manual mandates the 
least significant bit to be zeroed out. Failure to do so should result 
in an undefined instruction. With this change 
test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

2. VSTn instructions have a number of encoding constraints which are not 
implemented. I have added these using wrapper methods around the 
original custom decoder (incidentally - this is a huge poorly written 
method that should be cleaned up. I have left it as is since the changes 
would be much to hard to review).

Regards,
Mihai
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