[www] r180689 - Euro-LLVM-2013 schedule update: 'Implementing Data Layout Optimizations in LLVM Framework' is cancelled.
Arnaud A. de Grandmaison
arnaud.adegm at gmail.com
Sun Apr 28 14:23:11 PDT 2013
Author: aadg
Date: Sun Apr 28 16:23:09 2013
New Revision: 180689
URL: http://llvm.org/viewvc/llvm-project?rev=180689&view=rev
Log:
Euro-LLVM-2013 schedule update: 'Implementing Data Layout Optimizations in LLVM Framework' is cancelled.
Modified:
www/trunk/devmtg/2013-04/index.html
Modified: www/trunk/devmtg/2013-04/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2013-04/index.html?rev=180689&r1=180688&r2=180689&view=diff
==============================================================================
--- www/trunk/devmtg/2013-04/index.html (original)
+++ www/trunk/devmtg/2013-04/index.html Sun Apr 28 16:23:09 2013
@@ -177,10 +177,7 @@ A few words about the organization :
13:35 - 14:20</td>
<td>Dussane</td> <td>Talk : <a href="#talk8">lld - Solving the Linking Performance Problem</a></td> </tr> <tr>
<td>Résistants</td> <td>Talk : <a href="#talk13">An experimental framework for Pragma Handling in Clang</a></td> </tr>
- <tr> <td rowspan="2">
- 14:20 - 15:05</td>
- <td>Dussane</td> <td>Talk : <a href="#talk5">Debug Info - Status and Directions</a></td> </tr> <tr>
- <td>Résistants</td> <td>Talk : <a href="#talk11">Implementing Data Layout Optimizations in LLVM Framework</a></td> </tr>
+ <tr> <td>14:20 - 15:05</td> <td>Dussane</td> <td>Talk : <a href="#talk5">Debug Info - Status and Directions</a></td> </tr>
<tr> <td>15:05 - 16:05</td> <td>Dussane</td> <td>Tutorial : <a href="#tuto1">The Clang AST - a tutorial</a></td> </tr>
@@ -409,21 +406,6 @@ data types and plan to upstream the chan
</p>
<p>
-<b><a id="talk11">Implementing Data Layout Optimizations in LLVM Framework
-</a></b><br>
-<i>Prashantha Naduthota</i><br>
-The difference in speeds between processor and memory are increasing day by
-day. Compilers try to alleviate the same by different strategies.
-For regular array accesses in loops, array access patterns are modifed
-for better cache behaviour subject to program correctness.
-Large structure fields can be reordered for better cache behaviour
-by modifying the layout of the data. In this work, we discuss the different
-Data Layout Optimizations implemented in LLVM frame work to gain better
-memory behaviour. CPU 2006 SPEC benchmarks showed impressive gains upto 140
-percent because of the optimizations.
-</p>
-
-<p>
<b><a id="talk12">How to implement an LLVM Assembler - a tutorial
</a></b><br>
<i>Simon Cook - Embecosm</i><br>
More information about the llvm-commits
mailing list