[llvm] r174904 - Extend Hexagon hardware loop generation to handle various additional cases:

[Krzysztof Parzyszek]

On 4/26/2013 10:53 PM, Hal Finkel wrote:
>
> I'd found from working with the first version of this pass, ported to PPC, that I needed to add the counter register as live-in to all non-preheader loop blocks (or at least to LastMBB). Do you need to do something similar here? [for machine-code verification.]

Hi Hal,

Thanks for the additional comments---I just read them and I haven't 
thought about them in detail yet, but just to comment on the liveness 
remark above: the registers (SAn and LCn, n=0,1) that control hardware 
loop execution on Hexagon are marked as reserved, which (IIRC) exempts 
them from the liveness tracking.

On the other comments---you're most likely right.  The code has evolved 
from a simpler version, and some pieces of it that were needed earlier 
may no longer be necessary.  In the long run it should be refactored to 
common out the functionality that could be shared between architectures. 
  Unfortunately, the way the code is currently written is 
Hexagon-centric, and so each time you have to go through the porting 
process.

-Krzysztof

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