[PATCH] Allow ParserMatchClass attribute on RegisterClass

[Hal Finkel]

----- Original Message -----
> From: "Ulrich Weigand" <Ulrich.Weigand at de.ibm.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Commit Messages and Patches for LLVM" <llvm-commits at cs.uiuc.edu>
> Sent: Thursday, April 25, 2013 12:35:42 PM
> Subject: Re: [PATCH] Allow ParserMatchClass attribute on RegisterClass
> 
> Hal Finkel <hfinkel at anl.gov> wrote on 02.04.2013 15:27:16:
> 
> > ----- Original Message -----
> > > From: "Ulrich Weigand" <Ulrich.Weigand at de.ibm.com>
> > > To: "Hal Finkel" <hfinkel at anl.gov>
> 
> > > Hal, would you be OK with changing the PowerPC back-end to
> > > pervasively
> > > use RegisterOperand predicates instead of plain RegisterClass?
> >
> > Yes.
> >
> > >
> > > One question would be the naming; I guess as precedent for
> > > operand
> > > predicates is to be fully lower case, maybe it would make sense
> > > to
> > > create a RegisterOperand corresponding to every RegisterClass,
> > > where
> > > the name of the RegisterOperand is simply the lower-case version
> > > of
> > > the name of the RegisterClass?   E.g.
> > >    GPRC --> gprc
> > >    G8RC --> g8rc
> > >    VRRC --> vrrc
> > >
> > > (This has the additional advantage that a global
> > > search-and-replace
> > > will not mess up 80-column limits etc.)
> >
> > Sounds good to me.
> 
> Here's a patch that implements this.  Does this look OK?   If so,
> should
> I commit it right away or wait until the asm parser itself is ready?

LGTM. So long as we're sure that this is part of the final solution, then go ahead and commit. Can you please add a comment above the register operand definitions explaining their purpose.

Thanks again,
Hal

> 
> (See attached file: diff-llvm-asm-regclass)
> 
> Bye,
> Ulrich