[PATCH] Fix spilling of 64-bit paired registers (PR15676)

[Jakob Stoklund Olesen]

On Apr 20, 2013, at 6:43 AM, Tim Northover <t.p.northover at gmail.com> wrote:

> Hi,
> 
> This patch should fix PR15676, which turned out to be due to an
> incorrect LDMIA instruction being produced when spilling a 64-bit
> paired register (like you get from some inline assembly).
> 
> It looked like:
> 
> LDMIA <fi#4>, pred:0, pred:14, %noreg, ...
> 
> Where that first "pred:0" was added as some kind of offset for the
> frame, but the LDMIA instruction has no such offset.
> 
> This could obviously have caused a problem anywhere, it happened to
> strike first (in a Debug build) when examining the predicate (ARM code
> expected the second "pred" to be a register).
> 
> OK to commit?

LGTM.

Could you extend the test case to also require spilling at an offset from sp? I want to see the scavenger being used correctly.

Would it be better to use ldrd/strd?

Thanks,
/jakob