[Patch][Review Requested] Add peephole optimization to use LEA instructions of Intel Atom

[Du Toit, Stefanus]

Could you submit your patch to Phabricator
(http://llvm-reviews.chandlerc.com/)? It makes for easier reviewing.

I've done a very quick skim of this and have some comments below.

High level comment: should there be test cases for cases where the LEA
transformation should *not* happen?

Details below.

@@ -979,18 +979,8 @@
   if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
     return;
 
-  // If this is a two-address instruction, skip one of the register
operands.
[...]
-  }
+  unsigned CurOp = X86II::getOperandBias(Desc);
[...]
 
+  /// getOperandBias - If this is a two-address instruction,
+  /// skip one of the register operands.
+  /// FIXME: This should be handled during MCInst lowering.
+  inline int getOperandBias(const MCInstrDesc& Desc)
[...]
+  }

This is just refactoring, right? If so, commit this in a separate patch.

+  if (getOptLevel() != CodeGenOpt::None &&
+      getX86Subtarget().LEAusesAG()){
+    // this is needed for some Atom family members
+    addPass(createX86FixupLEAs());
+    ShouldPrint = true;
+  }


Comment seems out of place - if a sub target sets LEAusesAG(), this
applies; doesn't matter whether it's Atom or otherwise.



+  MachineInstr *X86convertToThreeAddress(MachineFunction::iterator &MFI,
+                                         MachineBasicBlock::iterator
&MBBI,
+                                         LiveVariables *LV,
+                                         bool AfterRegAlloc) const;



Why not just add a parameter with a default argument? Also, please
document the semantics of AfterRegAlloc.

+    const TargetInstrInfo *TII; // Machine instruction info.
+    //const TargetMachine *TM;
+    LiveVariables *LV;


Leftover commented out code.



--
Stefanus Du Toit <stefanus.du.toit at intel.com>
Intel Waterloo
Phone: 519-591-1738


From:  <Gurd>, Preston Gurd <preston.gurd at intel.com>
Date:  Tuesday, 9 April, 2013 10:34 AM
To:  "llvm-commits at cs.uiuc.edu" <llvm-commits at cs.uiuc.edu>
Subject:  FW: [Patch][Review Requested] Add peephole optimization to use
LEA	instructions of Intel Atom


PingŠ
 
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu]
On Behalf Of Gurd, Preston
Sent: Friday, April 05, 2013 6:07 PM
To: llvm-commits at cs.uiuc.edu
Subject: [Patch][Review Requested] Add peephole optimization to use LEA
instructions of Intel Atom


 
This patch adds a pass which runs after register allocation when an Intel
Atom processor is the target. The LEA instruction in the current Atom
processor is specifically optimized to work best when its result is to be
used as part of a
 memory address. This patch finds load or store instructions which use a
base and/or an index register. It looks for an instruction in the current
basic block which sets the base and/or index in the previous 5
instructions and then attempts to convert the instruction
 into an LEA, using the existing convertToThreeAddress code. For instance,
it could convert an add or a move into an LEA. Since the result of an LEA
is available earlier than the result of an ADD or a Move, there can be
less delay in starting the load or store
 which references the register.
 
Please review.
 
Thanks,
 
Preston
 
--
Preston Gurd <preston.gurd at intel.com>
  Intel Waterloo
  SSG/DPD/ECDL/DMP