FW: [Patch][Review Requested] Add peephole optimization to use LEA instructions of Intel Atom

[Gurd, Preston]

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From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Gurd, Preston
Sent: Friday, April 05, 2013 6:07 PM
To: llvm-commits at cs.uiuc.edu
Subject: [Patch][Review Requested] Add peephole optimization to use LEA instructions of Intel Atom

This patch adds a pass which runs after register allocation when an Intel Atom processor is the target. The LEA instruction in the current Atom processor is specifically optimized to work best when its result is to be used as part of a memory address. This patch finds load or store instructions which use a base and/or an index register. It looks for an instruction in the current basic block which sets the base and/or index in the previous 5 instructions and then attempts to convert the instruction into an LEA, using the existing convertToThreeAddress code. For instance, it could convert an add or a move into an LEA. Since the result of an LEA is available earlier than the result of an ADD or a Move, there can be less delay in starting the load or store which references the register.

Please review.

Thanks,

Preston

--
Preston Gurd <preston.gurd at intel.com<mailto:preston.gurd at intel.com>>
  Intel Waterloo
  SSG/DPD/ECDL/DMP

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