[llvm] r178407 - [mips] Define reg+imm load/store pattern templates.

[Akira Hatanaka]

Perhaps the commit message was unclear, but this patch doesn't change any
functionality. It just rewrites the existing patterns using the newly
defined pattern templates (LoadRegImmPat and StoreRegImmPat).

For example, using template LoadRegImmPat,

def : LoadRegImmPat<LWC1_P8, f32, load>;

expands to

def MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>;

, which is exactly what I had before I committed this patch.

r178408 has test cases which test patterns using LoadRegImmPat.

On Mon, Apr 1, 2013 at 7:30 AM, Rafael Espíndola <rafael.espindola at gmail.com
> wrote:

> Can you write a test for this?
>
> On 29 March 2013 22:01, Akira Hatanaka <ahatanaka at mips.com> wrote:
> > Author: ahatanak
> > Date: Fri Mar 29 21:01:48 2013
> > New Revision: 178407
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=178407&view=rev
> > Log:
> > [mips] Define reg+imm load/store pattern templates.
> >
> > Modified:
> >     llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> >     llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> >
> > Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=178407&r1=178406&r2=178407&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
> > +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Mar 29 21:01:48 2013
> > @@ -503,32 +503,27 @@ let Predicates = [IsFP64bit, HasStdEnc]
> >    def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
> >  }
> >
> > -// Load/Store patterns.
> > +// Patterns for loads/stores with a reg+imm operand.
> >  let AddedComplexity = 40 in {
> >    let Predicates = [IsN64, HasStdEnc] in {
> > -    def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>;
> > -    def : MipsPat<(store FGR32:$v, addrRegImm:$a),
> > -                  (SWC1_P8 FGR32:$v, addrRegImm:$a)>;
> > -    def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164_P8
> addrRegImm:$a)>;
> > -    def : MipsPat<(store FGR64:$v, addrRegImm:$a),
> > -                  (SDC164_P8 FGR64:$v, addrRegImm:$a)>;
> > +    def : LoadRegImmPat<LWC1_P8, f32, load>;
> > +    def : StoreRegImmPat<SWC1_P8, f32>;
> > +    def : LoadRegImmPat<LDC164_P8, f64, load>;
> > +    def : StoreRegImmPat<SDC164_P8, f64>;
> >    }
> >
> >    let Predicates = [NotN64, HasStdEnc] in {
> > -    def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1 addrRegImm:$a)>;
> > -    def : MipsPat<(store FGR32:$v, addrRegImm:$a),
> > -                  (SWC1 FGR32:$v, addrRegImm:$a)>;
> > +    def : LoadRegImmPat<LWC1, f32, load>;
> > +    def : StoreRegImmPat<SWC1, f32>;
> >    }
> >
> >    let Predicates = [NotN64, HasMips64, HasStdEnc] in {
> > -    def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164 addrRegImm:$a)>;
> > -    def : MipsPat<(store FGR64:$v, addrRegImm:$a),
> > -                  (SDC164 FGR64:$v, addrRegImm:$a)>;
> > +    def : LoadRegImmPat<LDC164, f64, load>;
> > +    def : StoreRegImmPat<SDC164, f64>;
> >    }
> >
> >    let Predicates = [NotN64, NotMips64, HasStdEnc] in {
> > -    def : MipsPat<(f64 (load addrRegImm:$a)), (LDC1 addrRegImm:$a)>;
> > -    def : MipsPat<(store AFGR64:$v, addrRegImm:$a),
> > -                  (SDC1 AFGR64:$v, addrRegImm:$a)>;
> > +    def : LoadRegImmPat<LDC1, f64, load>;
> > +    def : StoreRegImmPat<SDC1, f64>;
> >    }
> >  }
> >
> > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=178407&r1=178406&r2=178407&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Mar 29 21:01:48 2013
> > @@ -1102,6 +1102,13 @@ def LoadAddr32Imm : LoadAddressImm<"la",
> >  //  Arbitrary patterns that map to one or more instructions
> >
>  //===----------------------------------------------------------------------===//
> >
> > +// Load/store pattern templates.
> > +class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag
> Node> :
> > +  MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
> > +
> > +class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
> > +  MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v,
> addrRegImm:$a)>;
> > +
> >  // Small immediates
> >  def : MipsPat<(i32 immSExt16:$in),
> >                (ADDiu ZERO, imm:$in)>;
> >
> >
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