<div dir="ltr"><div><div>Perhaps the commit message was unclear, but this patch doesn't change any functionality. It just rewrites the existing patterns using the newly defined pattern templates (LoadRegImmPat and StoreRegImmPat).<br>
<br>For example, using template LoadRegImmPat,<br><br>def : LoadRegImmPat<LWC1_P8, f32, load>;<br>
<br>expands to<br><br>def MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>;<br>
<br></div>, which is exactly what I had before I committed this patch.<br><br></div>r178408 has test cases which test patterns using LoadRegImmPat.<br><br>
<div><div><div><div><div class="gmail_extra"><div class="gmail_quote">On Mon, Apr 1, 2013 at 7:30 AM, Rafael Espíndola <span dir="ltr"><<a href="mailto:rafael.espindola@gmail.com" target="_blank">rafael.espindola@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Can you write a test for this?<br>
<div class=""><div class="h5"><br>
On 29 March 2013 22:01, Akira Hatanaka <<a href="mailto:ahatanaka@mips.com">ahatanaka@mips.com</a>> wrote:<br>
> Author: ahatanak<br>
> Date: Fri Mar 29 21:01:48 2013<br>
> New Revision: 178407<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=178407&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=178407&view=rev</a><br>
> Log:<br>
> [mips] Define reg+imm load/store pattern templates.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/Mips/MipsInstrFPU.td<br>
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=178407&r1=178406&r2=178407&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=178407&r1=178406&r2=178407&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Mar 29 21:01:48 2013<br>
> @@ -503,32 +503,27 @@ let Predicates = [IsFP64bit, HasStdEnc]<br>
> def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;<br>
> }<br>
><br>
> -// Load/Store patterns.<br>
> +// Patterns for loads/stores with a reg+imm operand.<br>
> let AddedComplexity = 40 in {<br>
> let Predicates = [IsN64, HasStdEnc] in {<br>
> - def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>;<br>
> - def : MipsPat<(store FGR32:$v, addrRegImm:$a),<br>
> - (SWC1_P8 FGR32:$v, addrRegImm:$a)>;<br>
> - def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164_P8 addrRegImm:$a)>;<br>
> - def : MipsPat<(store FGR64:$v, addrRegImm:$a),<br>
> - (SDC164_P8 FGR64:$v, addrRegImm:$a)>;<br>
> + def : LoadRegImmPat<LWC1_P8, f32, load>;<br>
> + def : StoreRegImmPat<SWC1_P8, f32>;<br>
> + def : LoadRegImmPat<LDC164_P8, f64, load>;<br>
> + def : StoreRegImmPat<SDC164_P8, f64>;<br>
> }<br>
><br>
> let Predicates = [NotN64, HasStdEnc] in {<br>
> - def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1 addrRegImm:$a)>;<br>
> - def : MipsPat<(store FGR32:$v, addrRegImm:$a),<br>
> - (SWC1 FGR32:$v, addrRegImm:$a)>;<br>
> + def : LoadRegImmPat<LWC1, f32, load>;<br>
> + def : StoreRegImmPat<SWC1, f32>;<br>
> }<br>
><br>
> let Predicates = [NotN64, HasMips64, HasStdEnc] in {<br>
> - def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164 addrRegImm:$a)>;<br>
> - def : MipsPat<(store FGR64:$v, addrRegImm:$a),<br>
> - (SDC164 FGR64:$v, addrRegImm:$a)>;<br>
> + def : LoadRegImmPat<LDC164, f64, load>;<br>
> + def : StoreRegImmPat<SDC164, f64>;<br>
> }<br>
><br>
> let Predicates = [NotN64, NotMips64, HasStdEnc] in {<br>
> - def : MipsPat<(f64 (load addrRegImm:$a)), (LDC1 addrRegImm:$a)>;<br>
> - def : MipsPat<(store AFGR64:$v, addrRegImm:$a),<br>
> - (SDC1 AFGR64:$v, addrRegImm:$a)>;<br>
> + def : LoadRegImmPat<LDC1, f64, load>;<br>
> + def : StoreRegImmPat<SDC1, f64>;<br>
> }<br>
> }<br>
><br>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=178407&r1=178406&r2=178407&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=178407&r1=178406&r2=178407&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Mar 29 21:01:48 2013<br>
> @@ -1102,6 +1102,13 @@ def LoadAddr32Imm : LoadAddressImm<"la",<br>
> // Arbitrary patterns that map to one or more instructions<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> +// Load/store pattern templates.<br>
> +class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :<br>
> + MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;<br>
> +<br>
> +class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :<br>
> + MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;<br>
> +<br>
> // Small immediates<br>
> def : MipsPat<(i32 immSExt16:$in),<br>
> (ADDiu ZERO, imm:$in)>;<br>
><br>
><br>
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</div></div></blockquote></div><br></div></div></div></div></div></div>