[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Weiming Zhao]

Hi Renato,

 

GCC doesn’t do this correctly:

#APP

@ 4 "ldrd1.c" 1

                ldrd r4, [r1]

@ 0 "" 2

 

And even if we can let LLVM to expand %0 to two consecutive regs, it will
break cases like:

“ldrexd %0, %H0, 
” by emitting an extra reg (%H0 now becomes redundant). 

 

Thanks,

Weiming

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Renato Golin [mailto:renato.golin at linaro.org] 
Sent: Tuesday, March 26, 2013 12:16 PM
To: Zhao
Cc: Kristof Beyls; Eric Christopher; Måns Rullgård; Jim Grosbach; Jakob
Stoklund Olesen; LLVM Commits
Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

 

Hi Weiming,

 

Would be good to also have a test on Mans' original report (without the H
construct):

 

"A common pattern where llvm still fails is code using the abbreviated

syntax for LDRD and friends supported by gas:

 

    __asm__ ("ldrd %0, [%1]" : "=r"(a) : "r"(b));

 

Here the second destination register is implicitly one higher than the

first.  Because of this, the %H0 construct is never used, so the forced

even/odd allocation is skipped."

 

cheers,

--renato

 

 

On 26 March 2013 19:03, Weiming Zhao <weimingz at codeaurora.org> wrote:

Hi Renato, Kristof,

 

I added two test cases. One for ldrd, one for strd.

Please help ot review them. 

 

Thanks,

Weiming

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Kristof Beyls [mailto:kristof.beyls at arm.com] 
Sent: Tuesday, March 26, 2013 1:28 AM
To: 'Renato Golin'; Zhao


Cc: Eric Christopher; Måns Rullgård; Jim Grosbach; Jakob Stoklund Olesen;
LLVM Commits

Subject: RE: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

 

Hi Renato, Weiming,

 

I’m afraid I don’t know too much about inline assembly details, so can’t
really do a good code review.

That being said, I agree with Renato that there should be regression tests
added that test the changed functionality.

Apart from ensuring the functionality doesn’t get broken by accident in the
future, I find it also helps reviewers in
understanding the exact behavioural changes that are intended.

 

Thanks,

 

Kristof

 

From: Renato Golin [mailto:renato.golin at linaro.org] 

Sent: 25 March 2013 11:17
To: Zhao
Cc: Eric Christopher; Måns Rullgård; Jim Grosbach; Jakob Stoklund Olesen;
LLVM Commits; Kristof Beyls

Subject: Re: [LLVMdev] Problems with 64-bit register operands of inline asm
on ARM

 

On 14 March 2013 23:15, Weiming Zhao <weimingz at codeaurora.org> wrote:

Hi,

 

Attached is the patch to enable GPRPair for all i64 operands for ARM mode.

I let ASMPrinter to print subregs for ldm/stm and support ‘Q’ modifier.

I also extend SelectInlineAsm to support tied-def-use regs.

 

Hi Weiming,

 

It looks reasonable to me, have you ran the test-suite with it? Would also
be good to add some extra check-all tests, if possible.

 

Kristof,

 

Any issues on your side?

 

cheers,

--renato

 

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