[PATCH] Add HLE target feature

[Michael Liao]

I'm referring this document,
https://www.power.org/documentation/power-isa-transactional-memory/

Technically, lock elision could even be implemented upon STM. Ofc, it's
not practical one.

- michael

On Wed, 2013-02-27 at 18:39 -0600, Krzysztof Parzyszek wrote:
> On 2/27/2013 6:23 PM, Jeffrey Yasskin wrote:
> >
> > I'm curious how Power can take advantage of HLE metadata. Could you
> > post an example LLVM IR sequence and its expansion into both x86 and
> > Power assembly?
> 
> A2 has some support for "writeless" locks: there is a "ldawx" 
> instruction that sets a watchpoint associated with the cache line from 
> which the load occured. If other threads write into that cache line, the 
> watchpoint is cleared.  The thread can then test if all the watchpoints 
> are still set (or if one or more has been cleared).
> 
> This is not a part of the PowerPC ISA, btw.
> 
> -Krzysztof
>