[PATCH] Add HLE target feature

[Jeffrey Yasskin]

On Wed, Feb 27, 2013 at 4:14 PM, Michael Liao <michael.liao at intel.com> wrote:
> Hi Krzysztof
>
> On Wed, 2013-02-27 at 17:50 -0600, Krzysztof Parzyszek wrote:
>> On 2/27/2013 5:09 PM, Michael Liao wrote:
>> >
>> > "LLVM Atomic Instructions and Concurrency Guide" puts more details on
>> > why atomic instructions are added in LLVM IR and optimizations around
>> > it. For HLE support, you could treat an enhancement on atomic
>> > instruction by taking advantage of hardware support or TM support, the
>> > current approach is to add hint in atomic instructions already existed
>> > in LLVM IR to help backend generate proper code.
>>
>> This sort of thing belongs in the X86 backend, not LLVM IR.  The IR
>> already contains atomic instructions, and the decision of how to best
>> implement them on a particular platform is best left to the individual
>
> HLE is not an X86-specific feature. Any hardware with TM support, e.g.
> Power (thanks to Hal once pointed out), could support that but possibly
> use different names, such as TLE (transactional lock elision) or SLE
> (speculative lock elision) or whatever.

I'm curious how Power can take advantage of HLE metadata. Could you
post an example LLVM IR sequence and its expansion into both x86 and
Power assembly?