[llvm] r174920 - Added 0x0D to 2-byte opcode extension table for prefetch* variants

[Kay Tiong Khoo]

Sorry - added in r174979.

This still needs some work because the existing code is for the deprecated
3DNow ISA - but this appears to be on by default for all x86 targets. And
Intel is apparently resurrecting just 1 of the 2 opcodes / instructions for
their next CPUs with a "PRFCHW" CPUID bit.


On Mon, Feb 11, 2013 at 5:31 PM, Eric Christopher <echristo at gmail.com>wrote:

> Testcases?
>
> -eric
>
>
> On Mon, Feb 11, 2013 at 4:19 PM, Kay Tiong Khoo <kkhoo at perfwizard.com>wrote:
>
>> Author: kkhoo
>> Date: Mon Feb 11 18:19:12 2013
>> New Revision: 174920
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=174920&view=rev
>> Log:
>> Added 0x0D to 2-byte opcode extension table for prefetch* variants
>> Fixed decode of existing 3dNow prefetchw instruction
>> Intel is scheduled to add a compatible prefetchw (same encoding) to
>> future CPUs
>>
>> Modified:
>>     llvm/trunk/lib/Target/X86/X86Instr3DNow.td
>>     llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
>>
>> Modified: llvm/trunk/lib/Target/X86/X86Instr3DNow.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr3DNow.td?rev=174920&r1=174919&r2=174920&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Instr3DNow.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86Instr3DNow.td Mon Feb 11 18:19:12 2013
>> @@ -87,12 +87,10 @@ defm PMULHRW  : I3DNow_binop_rm_int<0xB7
>>  def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
>> [(int_x86_mmx_femms)]>;
>>
>>  def PREFETCH  : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
>> -                       "prefetch $addr", []>;
>> +                       "prefetch\t$addr", []>;
>>
>> -// FIXME: Diassembler gets a bogus decode conflict.
>> -let isAsmParserOnly = 1 in
>>  def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
>> -                       "prefetchw $addr", []>;
>> +                       "prefetchw\t$addr", []>;
>>
>>  // "3DNowA" instructions
>>  defm PF2IW    : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
>>
>> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=174920&r1=174919&r2=174920&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
>> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Feb 11
>> 18:19:12 2013
>> @@ -119,6 +119,7 @@ namespace X86Local {
>>  #define TWO_BYTE_EXTENSION_TABLES \
>>    EXTENSION_TABLE(00)             \
>>    EXTENSION_TABLE(01)             \
>> +  EXTENSION_TABLE(0d)             \
>>    EXTENSION_TABLE(18)             \
>>    EXTENSION_TABLE(71)             \
>>    EXTENSION_TABLE(72)             \
>>
>>
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>
>
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