Sorry - added in r174979. <br><br>This still needs some work because the existing code is for the deprecated 3DNow ISA - but this appears to be on by default for all x86 targets. And Intel is apparently resurrecting just 1 of the 2 opcodes / instructions for their next CPUs with a "PRFCHW" CPUID bit.<span style="font-size:9.000000pt;font-family:'NeoSansIntel'"></span><br>
<br><br><div class="gmail_quote">On Mon, Feb 11, 2013 at 5:31 PM, Eric Christopher <span dir="ltr"><<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr">Testcases?<span class="HOEnZb"><font color="#888888"><div><br></div><div>-eric</div></font></span></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Feb 11, 2013 at 4:19 PM, Kay Tiong Khoo <span dir="ltr"><<a href="mailto:kkhoo@perfwizard.com" target="_blank">kkhoo@perfwizard.com</a>></span> wrote:<br>

<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: kkhoo<br>
Date: Mon Feb 11 18:19:12 2013<br>
New Revision: 174920<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=174920&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=174920&view=rev</a><br>
Log:<br>
Added 0x0D to 2-byte opcode extension table for prefetch* variants<br>
Fixed decode of existing 3dNow prefetchw instruction<br>
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/X86Instr3DNow.td<br>
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Instr3DNow.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr3DNow.td?rev=174920&r1=174919&r2=174920&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr3DNow.td?rev=174920&r1=174919&r2=174920&view=diff</a><br>


==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Instr3DNow.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Instr3DNow.td Mon Feb 11 18:19:12 2013<br>
@@ -87,12 +87,10 @@ defm PMULHRW  : I3DNow_binop_rm_int<0xB7<br>
 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;<br>
<br>
 def PREFETCH  : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),<br>
-                       "prefetch $addr", []>;<br>
+                       "prefetch\t$addr", []>;<br>
<br>
-// FIXME: Diassembler gets a bogus decode conflict.<br>
-let isAsmParserOnly = 1 in<br>
 def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),<br>
-                       "prefetchw $addr", []>;<br>
+                       "prefetchw\t$addr", []>;<br>
<br>
 // "3DNowA" instructions<br>
 defm PF2IW    : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;<br>
<br>
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=174920&r1=174919&r2=174920&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=174920&r1=174919&r2=174920&view=diff</a><br>


==============================================================================<br>
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Feb 11 18:19:12 2013<br>
@@ -119,6 +119,7 @@ namespace X86Local {<br>
 #define TWO_BYTE_EXTENSION_TABLES \<br>
   EXTENSION_TABLE(00)             \<br>
   EXTENSION_TABLE(01)             \<br>
+  EXTENSION_TABLE(0d)             \<br>
   EXTENSION_TABLE(18)             \<br>
   EXTENSION_TABLE(71)             \<br>
   EXTENSION_TABLE(72)             \<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br>