[llvm] r174633 - R600/SI: Make sample intrinsic address parameter type overloaded.
Tom Stellard
thomas.stellard at amd.com
Thu Feb 7 09:02:13 PST 2013
Author: tstellar
Date: Thu Feb 7 11:02:13 2013
New Revision: 174633
URL: http://llvm.org/viewvc/llvm-project?rev=174633&view=rev
Log:
R600/SI: Make sample intrinsic address parameter type overloaded.
Handle vectors of 1 to 16 integers.
Change the intrinsic names to prevent the wrong one from being selected at
runtime due to the overloading.
Patch By: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Modified:
llvm/trunk/lib/Target/R600/SIInstrInfo.td
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/lib/Target/R600/SIIntrinsics.td
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=174633&r1=174632&r2=174633&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Thu Feb 7 11:02:13 2013
@@ -519,7 +519,7 @@ class MIMG_Load_Helper <bits<7> op, stri
op,
(outs VReg_128:$vdata),
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
- i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
+ i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
asm,
[]> {
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=174633&r1=174632&r2=174633&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Thu Feb 7 11:02:13 2013
@@ -1186,33 +1186,49 @@ def : Pat <
VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3)
>;
-/* int_SI_sample */
-def : Pat <
- (int_SI_sample imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
- (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
- SReg_256:$rsrc, SReg_128:$sampler)
->;
+/* int_SI_sample for simple 1D texture lookup */
def : Pat <
- (int_SI_sample imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
- (IMAGE_SAMPLE imm:$writemask, 1, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
+ (int_SI_sample imm:$writemask, (v1i32 VReg_32:$addr),
+ SReg_256:$rsrc, SReg_128:$sampler, imm),
+ (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
+ (i32 (COPY_TO_REGCLASS VReg_32:$addr, VReg_32)),
SReg_256:$rsrc, SReg_128:$sampler)
>;
-/* int_SI_sample_lod */
-def : Pat <
- (int_SI_sample_lod imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
- (IMAGE_SAMPLE_L imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
- SReg_256:$rsrc, SReg_128:$sampler)
+class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
+ ValueType addr_type> : Pat <
+ (name imm:$writemask, (addr_type addr_class:$addr),
+ SReg_256:$rsrc, SReg_128:$sampler, imm),
+ (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
+ (EXTRACT_SUBREG addr_class:$addr, sub0),
+ SReg_256:$rsrc, SReg_128:$sampler)
>;
-/* int_SI_sample_bias */
-def : Pat <
- (int_SI_sample_bias imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
- (IMAGE_SAMPLE_B imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
- SReg_256:$rsrc, SReg_128:$sampler)
+class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
+ ValueType addr_type> : Pat <
+ (name imm:$writemask, (addr_type addr_class:$addr),
+ SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
+ (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0,
+ (EXTRACT_SUBREG addr_class:$addr, sub0),
+ SReg_256:$rsrc, SReg_128:$sampler)
>;
+/* int_SI_sample* for texture lookups consuming more address parameters */
+multiclass SamplePatterns<RegisterClass addr_class, ValueType addr_type> {
+ def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
+ def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
+
+ def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>;
+
+ def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>;
+}
+
+defm : SamplePatterns<VReg_64, v2i32>;
+defm : SamplePatterns<VReg_128, v4i32>;
+defm : SamplePatterns<VReg_256, v8i32>;
+defm : SamplePatterns<VReg_512, v16i32>;
+
def CLAMP_SI : CLAMP<VReg_32>;
def FABS_SI : FABS<VReg_32>;
def FNEG_SI : FNEG<VReg_32>;
Modified: llvm/trunk/lib/Target/R600/SIIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIIntrinsics.td?rev=174633&r1=174632&r2=174633&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIIntrinsics.td (original)
+++ llvm/trunk/lib/Target/R600/SIIntrinsics.td Thu Feb 7 11:02:13 2013
@@ -22,11 +22,11 @@ let TargetPrefix = "SI", isTarget = 1 in
def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_i16_ty, llvm_i32_ty], [IntrReadMem]> ;
def int_SI_wqm : Intrinsic <[], [], []>;
- class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrReadMem]>;
+ class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrReadMem]>;
def int_SI_sample : Sample;
- def int_SI_sample_bias : Sample;
- def int_SI_sample_lod : Sample;
+ def int_SI_sampleb : Sample;
+ def int_SI_samplel : Sample;
/* Interpolation Intrinsics */
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