[llvm-commits] [llvm] r170436 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/PowerPC/in-asm-f64-reg.ll

[Rafael Espíndola]

The testcase can be simplified, no? For example, you probably only need one
basic block.
On Dec 18, 2012 12:53 PM, "Hal Finkel" <hfinkel at anl.gov> wrote:

> Author: hfinkel
> Date: Tue Dec 18 11:50:58 2012
> New Revision: 170436
>
> URL: http://llvm.org/viewvc/llvm-project?rev=170436&view=rev
> Log:
> Check multiple register classes for inline asm tied registers
>
> A register can be associated with several distinct register classes.
> For example, on PPC, the floating point registers are each associated with
> both F4RC (which holds f32) and F8RC (which holds f64). As a result, this
> code
> would fail when provided with a floating point register and an f64 operand
> because it would happen to find the register in the F4RC class first and
> return that. From the F4RC class, SDAG would extract f32 as the register
> type and then assert because of the invalid implied conversion between
> the f64 value and the f32 register.
>
> Instead, search all register classes. If a register class containing the
> the requested register has the requested type, then return that register
> class. Otherwise, as before, return the first register class found that
> contains the requested register.
>
> Added:
>     llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=170436&r1=170435&r2=170436&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Dec 18
> 11:50:58 2012
> @@ -2829,6 +2829,9 @@
>    // Remove the braces from around the name.
>    StringRef RegName(Constraint.data()+1, Constraint.size()-2);
>
> +  std::pair<unsigned, const TargetRegisterClass*> R =
> +    std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
> +
>    // Figure out which register class contains this reg.
>    const TargetRegisterInfo *RI = TM.getRegisterInfo();
>    for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
> @@ -2842,12 +2845,22 @@
>
>      for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
>           I != E; ++I) {
> -      if (RegName.equals_lower(RI->getName(*I)))
> -        return std::make_pair(*I, RC);
> +      if (RegName.equals_lower(RI->getName(*I))) {
> +        std::pair<unsigned, const TargetRegisterClass*> S =
> +          std::make_pair(*I, RC);
> +
> +        // If this register class has the requested value type, return it,
> +        // otherwise keep searching and return the first class found
> +        // if no other is found which explicitly has the requested type.
> +        if (RC->hasType(VT))
> +          return S;
> +        else if (!R.second)
> +          R = S;
> +      }
>      }
>    }
>
> -  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
> +  return R;
>  }
>
>
>  //===----------------------------------------------------------------------===//
>
> Added: llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll?rev=170436&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll Tue Dec 18 11:50:58
> 2012
> @@ -0,0 +1,22 @@
> +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
> +
> +target datalayout =
> "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
> +target triple = "powerpc64-bgq-linux"
> +
> +define void @_Z15quad_copy_1024nPcS_m() nounwind {
> +; CHECK: @_Z15quad_copy_1024nPcS_m
> +
> +entry:
> +  br i1 undef, label %short_msg, label %if.end
> +
> +if.end:                                           ; preds = %entry
> +  %0 = tail call double* asm sideeffect "qvstfdux $2,$0,$1",
> "=b,{r7},{f11},0,~{memory}"(i32 64, double undef, double* undef) nounwind,
> !srcloc !0
> +  unreachable
> +
> +; CHECK: qvstfdux 11,{{[0-9]+}},7
> +
> +short_msg:                                        ; preds = %entry
> +  ret void
> +}
> +
> +!0 = metadata !{i32 -2147422199}
>
>
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