<p dir="ltr">The testcase can be simplified, no? For example, you probably only need one basic block.</p>
<div class="gmail_quote">On Dec 18, 2012 12:53 PM, "Hal Finkel" <<a href="mailto:hfinkel@anl.gov">hfinkel@anl.gov</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: hfinkel<br>
Date: Tue Dec 18 11:50:58 2012<br>
New Revision: 170436<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=170436&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=170436&view=rev</a><br>
Log:<br>
Check multiple register classes for inline asm tied registers<br>
<br>
A register can be associated with several distinct register classes.<br>
For example, on PPC, the floating point registers are each associated with<br>
both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code<br>
would fail when provided with a floating point register and an f64 operand<br>
because it would happen to find the register in the F4RC class first and<br>
return that. From the F4RC class, SDAG would extract f32 as the register<br>
type and then assert because of the invalid implied conversion between<br>
the f64 value and the f32 register.<br>
<br>
Instead, search all register classes. If a register class containing the<br>
the requested register has the requested type, then return that register<br>
class. Otherwise, as before, return the first register class found that<br>
contains the requested register.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=170436&r1=170435&r2=170436&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=170436&r1=170435&r2=170436&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Dec 18 11:50:58 2012<br>
@@ -2829,6 +2829,9 @@<br>
// Remove the braces from around the name.<br>
StringRef RegName(Constraint.data()+1, Constraint.size()-2);<br>
<br>
+ std::pair<unsigned, const TargetRegisterClass*> R =<br>
+ std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));<br>
+<br>
// Figure out which register class contains this reg.<br>
const TargetRegisterInfo *RI = TM.getRegisterInfo();<br>
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),<br>
@@ -2842,12 +2845,22 @@<br>
<br>
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();<br>
I != E; ++I) {<br>
- if (RegName.equals_lower(RI->getName(*I)))<br>
- return std::make_pair(*I, RC);<br>
+ if (RegName.equals_lower(RI->getName(*I))) {<br>
+ std::pair<unsigned, const TargetRegisterClass*> S =<br>
+ std::make_pair(*I, RC);<br>
+<br>
+ // If this register class has the requested value type, return it,<br>
+ // otherwise keep searching and return the first class found<br>
+ // if no other is found which explicitly has the requested type.<br>
+ if (RC->hasType(VT))<br>
+ return S;<br>
+ else if (!R.second)<br>
+ R = S;<br>
+ }<br>
}<br>
}<br>
<br>
- return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));<br>
+ return R;<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll?rev=170436&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll?rev=170436&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/in-asm-f64-reg.ll Tue Dec 18 11:50:58 2012<br>
@@ -0,0 +1,22 @@<br>
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s<br>
+<br>
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"<br>
+target triple = "powerpc64-bgq-linux"<br>
+<br>
+define void @_Z15quad_copy_1024nPcS_m() nounwind {<br>
+; CHECK: @_Z15quad_copy_1024nPcS_m<br>
+<br>
+entry:<br>
+ br i1 undef, label %short_msg, label %if.end<br>
+<br>
+if.end: ; preds = %entry<br>
+ %0 = tail call double* asm sideeffect "qvstfdux $2,$0,$1", "=b,{r7},{f11},0,~{memory}"(i32 64, double undef, double* undef) nounwind, !srcloc !0<br>
+ unreachable<br>
+<br>
+; CHECK: qvstfdux 11,{{[0-9]+}},7<br>
+<br>
+short_msg: ; preds = %entry<br>
+ ret void<br>
+}<br>
+<br>
+!0 = metadata !{i32 -2147422199}<br>
<br>
<br>
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</blockquote></div>