[llvm-commits] [PATCH] ARM: Add vaddl/vsubl intrinsics

[Tim Northover]

> +def : Pat<(v4i32 (NEONvaddlu (v4i16 DPR:$src1), (v4i16 DPR:$src2))),
> +          (v4i32 (VADDLuv4i32 (v4i16 DPR:$src1), (v4i16 DPR:$src2)))>;
> +def : Pat<(v8i16 (NEONvaddlu (v8i8 DPR:$src1), (v8i8 DPR:$src2))),
> +          (v8i16 (VADDLuv8i16 (v8i8 DPR:$src1), (v8i8 DPR:$src2)))>;
> +def : Pat<(v2i64 (NEONvaddlu (v2i32 DPR:$src1), (v2i32 DPR:$src2))),
> +          (v2i64 (VADDLuv2i64 (v2i32 DPR:$src1), (v2i32 DPR:$src2)))>;
>
> I'm not a tablegen expert, but I think there's a better way of doing
> this... Tim, can you comment on that?

The type annotations seem a little extravagant (you should be able to
specify vNiM just once for input and possibly output if SDTARMVMULL is
defined appropriately), but I think the three patterns are necessary.
TableGen needs any pattern to have well-defined types, I believe. It
can't just instantiate a pattern over all sane types.

In summary: the quibbles I do have here could well come down to style
rather than objective reality.

Tim.