[llvm-commits] [llvm] r169536 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
Evan Cheng
evan.cheng at apple.com
Thu Dec 6 14:11:45 PST 2012
On Dec 6, 2012, at 1:03 PM, Matt Beaumont-Gay <matthewbg at google.com> wrote:
>
> GCC's -Woverloaded-virtual complains thusly:
> In file included from llvm/lib/Target/ARM/ARMISelLowering.h:23:0,
> from llvm/lib/Target/ARM/ARMTargetMachine.h:18,
> from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
> llvm/include/llvm/Target/TargetLowering.h:1708:16: error: 'virtual
> bool llvm::TargetLowering::isZExtFree(llvm::Type*, llvm::Type*) const'
> was hidden [-Werror=overloaded-virtual]
> In file included from llvm/lib/Target/ARM/ARMTargetMachine.h:18:0,
> from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
> llvm/lib/Target/ARM/ARMISelLowering.h:297:18: error: by 'virtual
> bool llvm::ARMTargetLowering::isZExtFree(llvm::SDValue, llvm::EVT)
> const' [-Werror=overloaded-virtual]
> In file included from llvm/lib/Target/ARM/ARMISelLowering.h:23:0,
> from llvm/lib/Target/ARM/ARMTargetMachine.h:18,
> from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
> llvm/include/llvm/Target/TargetLowering.h:1712:16: error: 'virtual
> bool llvm::TargetLowering::isZExtFree(llvm::EVT, llvm::EVT) const' was
> hidden [-Werror=overloaded-virtual]
> In file included from llvm/lib/Target/ARM/ARMTargetMachine.h:18:0,
> from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
> llvm/lib/Target/ARM/ARMISelLowering.h:297:18: error: by 'virtual
> bool llvm::ARMTargetLowering::isZExtFree(llvm::SDValue, llvm::EVT)
> const' [-Werror=overloaded-virtual]
That seems like a bug in GCC to me. It's totally unnecessary to add the other two isZExtFree() to ARMTargetLowerting.
clang -Woverloaded-virtual get this right.
Evan
>
>> /// isLegalAddressingMode - Return true if the addressing mode represented
>> /// by AM is legal for this target, for a load/store of the specified type.
>> virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
>> @@ -333,11 +335,6 @@
>> const SelectionDAG &DAG,
>> unsigned Depth) const;
>>
>> - virtual void computeMaskedBitsForAnyExtend(const SDValue Op,
>> - APInt &KnownZero,
>> - APInt &KnownOne,
>> - const SelectionDAG &DAG,
>> - unsigned Depth) const;
>>
>> virtual bool ExpandInlineAsm(CallInst *CI) const;
>>
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=169536&r1=169535&r2=169536&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 6 13:13:27 2012
>> @@ -12142,6 +12142,30 @@
>> return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
>> }
>>
>> +bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
>> + EVT VT1 = Val.getValueType();
>> + if (isZExtFree(VT1, VT2))
>> + return true;
>> +
>> + if (Val.getOpcode() != ISD::LOAD)
>> + return false;
>> +
>> + if (!VT1.isSimple() || !VT1.isInteger() ||
>> + !VT2.isSimple() || !VT2.isInteger())
>> + return false;
>> +
>> + switch (VT1.getSimpleVT().SimpleTy) {
>> + default: break;
>> + case MVT::i8:
>> + case MVT::i16:
>> + case MVT::i32:
>> + // X86 has 8, 16, and 32-bit zero-extending loads.
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
>> // i16 instructions are longer (0x66 prefix) and potentially slower.
>> return !(VT1 == MVT::i32 && VT2 == MVT::i16);
>> @@ -14093,38 +14117,6 @@
>> }
>> }
>>
>> -void X86TargetLowering::computeMaskedBitsForAnyExtend(const SDValue Op,
>> - APInt &KnownZero,
>> - APInt &KnownOne,
>> - const SelectionDAG &DAG,
>> - unsigned Depth) const {
>> - unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
>> - if (Op.getOpcode() == ISD::ANY_EXTEND) {
>> - // Implemented as a zero_extend except for i16 -> i32
>> - EVT InVT = Op.getOperand(0).getValueType();
>> - unsigned InBits = InVT.getScalarType().getSizeInBits();
>> - KnownZero = KnownZero.trunc(InBits);
>> - KnownOne = KnownOne.trunc(InBits);
>> - DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
>> - KnownZero = KnownZero.zext(BitWidth);
>> - KnownOne = KnownOne.zext(BitWidth);
>> - if (BitWidth != 32 || InBits != 16) {
>> - APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits);
>> - KnownZero |= NewBits;
>> - }
>> - return;
>> - } else if (ISD::isEXTLoad(Op.getNode())) {
>> - // Implemented as zextloads or implicitly zero-extended (i32 -> i64)
>> - LoadSDNode *LD = cast<LoadSDNode>(Op);
>> - EVT VT = LD->getMemoryVT();
>> - unsigned MemBits = VT.getScalarType().getSizeInBits();
>> - KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
>> - return;
>> - }
>> -
>> - assert(0 && "Expecting an ANY_EXTEND or extload!");
>> -}
>> -
>> unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
>> unsigned Depth) const {
>> // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=169536&r1=169535&r2=169536&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Dec 6 13:13:27 2012
>> @@ -558,12 +558,6 @@
>> const SelectionDAG &DAG,
>> unsigned Depth = 0) const;
>>
>> - virtual void computeMaskedBitsForAnyExtend(const SDValue Op,
>> - APInt &KnownZero,
>> - APInt &KnownOne,
>> - const SelectionDAG &DAG,
>> - unsigned Depth) const;
>> -
>> // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
>> // operation that are sign bits.
>> virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
>> @@ -634,6 +628,7 @@
>> /// result out to 64 bits.
>> virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
>> virtual bool isZExtFree(EVT VT1, EVT VT2) const;
>> + virtual bool isZExtFree(SDValue Val, EVT VT2) const;
>>
>> /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
>> /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
>>
>>
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