[llvm-commits] [llvm] r169536 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
Matt Beaumont-Gay
matthewbg at google.com
Thu Dec 6 13:03:28 PST 2012
On Thu, Dec 6, 2012 at 11:13 AM, Evan Cheng <evan.cheng at apple.com> wrote:
> Author: evancheng
> Date: Thu Dec 6 13:13:27 2012
> New Revision: 169536
>
> URL: http://llvm.org/viewvc/llvm-project?rev=169536&view=rev
> Log:
> Replace r169459 with something safer. Rather than having computeMaskedBits to
> understand target implementation of any_extend / extload, just generate
> zero_extend in place of any_extend for liveouts when the target knows the
> zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz).
>
> rdar://12771555
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetLowering.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Dec 6 13:13:27 2012
> @@ -935,16 +935,6 @@
> const SelectionDAG &DAG,
> unsigned Depth = 0) const;
>
> - /// computeMaskedBitsForAnyExtend - Since each target implement ANY_EXTEND
> - /// and ExtLoad nodes specifically, let the target determine which of the bits
> - /// specified in Mask are known to be either zero or one and return them in
> - /// the KnownZero/KnownOne bitsets.
> - virtual void computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth = 0) const;
> -
> /// ComputeNumSignBitsForTargetNode - This method can be implemented by
> /// targets that want to expose additional information about sign bits to the
> /// DAG Combiner.
> @@ -1723,6 +1713,13 @@
> return false;
> }
>
> + /// isZExtFree - Return true if zero-extending the specific node Val to type
> + /// VT2 is free (either because it's implicitly zero-extended such as ARM
> + /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
> + virtual bool isZExtFree(SDValue Val, EVT VT2) const {
> + return isZExtFree(Val.getValueType(), VT2);
> + }
> +
> /// isFNegFree - Return true if an fneg operation is free to the point where
> /// it is never worthwhile to replace it with a bitwise operation.
> virtual bool isFNegFree(EVT) const {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Dec 6 13:13:27 2012
> @@ -1930,8 +1930,6 @@
> KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
> } else if (const MDNode *Ranges = LD->getRanges()) {
> computeMaskedBitsLoad(*Ranges, KnownZero);
> - } else if (ISD::isEXTLoad(Op.getNode())) {
> - TLI.computeMaskedBitsForAnyExtend(Op, KnownZero, KnownOne, *this, Depth);
> }
> return;
> }
> @@ -1974,7 +1972,13 @@
> return;
> }
> case ISD::ANY_EXTEND: {
> - TLI.computeMaskedBitsForAnyExtend(Op, KnownZero, KnownOne, *this, Depth);
> + EVT InVT = Op.getOperand(0).getValueType();
> + unsigned InBits = InVT.getScalarType().getSizeInBits();
> + KnownZero = KnownZero.trunc(InBits);
> + KnownOne = KnownOne.trunc(InBits);
> + ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
> + KnownZero = KnownZero.zext(BitWidth);
> + KnownOne = KnownOne.zext(BitWidth);
> return;
> }
> case ISD::TRUNCATE: {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Dec 6 13:13:27 2012
> @@ -769,9 +769,11 @@
> EVT ValueVT = ValueVTs[Value];
> unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
> EVT RegisterVT = RegVTs[Value];
> + ISD::NodeType ExtendKind =
> + TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
>
> getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
> - &Parts[Part], NumParts, RegisterVT, V);
> + &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
> Part += NumParts;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Dec 6 13:13:27 2012
> @@ -1856,30 +1856,6 @@
> KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
> }
>
> -void TargetLowering::computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth) const {
> - unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
> - if (Op.getOpcode() == ISD::ANY_EXTEND) {
> - EVT InVT = Op.getOperand(0).getValueType();
> - unsigned InBits = InVT.getScalarType().getSizeInBits();
> - KnownZero = KnownZero.trunc(InBits);
> - KnownOne = KnownOne.trunc(InBits);
> - DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
> - KnownZero = KnownZero.zext(BitWidth);
> - KnownOne = KnownOne.zext(BitWidth);
> - return;
> - } else if (ISD::isEXTLoad(Op.getNode())) {
> - KnownZero = KnownOne = APInt(BitWidth, 0);
> - return;
> - }
> -
> - assert(0 && "Expecting an ANY_EXTEND or extload!");
> -}
> -
> -
> /// ComputeNumSignBitsForTargetNode - This method can be implemented by
> /// targets that want to expose additional information about sign bits to the
> /// DAG Combiner.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec 6 13:13:27 2012
> @@ -9462,6 +9462,27 @@
> return MVT::Other;
> }
>
> +bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
> + if (Val.getOpcode() != ISD::LOAD)
> + return false;
> +
> + EVT VT1 = Val.getValueType();
> + if (!VT1.isSimple() || !VT1.isInteger() ||
> + !VT2.isSimple() || !VT2.isInteger())
> + return false;
> +
> + switch (VT1.getSimpleVT().SimpleTy) {
> + default: break;
> + case MVT::i1:
> + case MVT::i8:
> + case MVT::i16:
> + // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
> + return true;
> + }
> +
> + return false;
> +}
> +
> static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
> if (V < 0)
> return false;
> @@ -9878,36 +9899,6 @@
> }
> }
>
> -void ARMTargetLowering::computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth) const {
> - unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
> - if (Op.getOpcode() == ISD::ANY_EXTEND) {
> - // Implemented as a zero_extend.
> - EVT InVT = Op.getOperand(0).getValueType();
> - unsigned InBits = InVT.getScalarType().getSizeInBits();
> - KnownZero = KnownZero.trunc(InBits);
> - KnownOne = KnownOne.trunc(InBits);
> - DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
> - KnownZero = KnownZero.zext(BitWidth);
> - KnownOne = KnownOne.zext(BitWidth);
> - APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits);
> - KnownZero |= NewBits;
> - return;
> - } else if (ISD::isEXTLoad(Op.getNode())) {
> - // Implemented as zextloads.
> - LoadSDNode *LD = cast<LoadSDNode>(Op);
> - EVT VT = LD->getMemoryVT();
> - unsigned MemBits = VT.getScalarType().getSizeInBits();
> - KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
> - return;
> - }
> -
> - assert(0 && "Expecting an ANY_EXTEND or extload!");
> -}
> -
> //===----------------------------------------------------------------------===//
> // ARM Inline Assembly Support
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Dec 6 13:13:27 2012
> @@ -294,6 +294,8 @@
> bool MemcpyStrSrc,
> MachineFunction &MF) const;
>
> + virtual bool isZExtFree(SDValue Val, EVT VT2) const;
> +
GCC's -Woverloaded-virtual complains thusly:
In file included from llvm/lib/Target/ARM/ARMISelLowering.h:23:0,
from llvm/lib/Target/ARM/ARMTargetMachine.h:18,
from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
llvm/include/llvm/Target/TargetLowering.h:1708:16: error: 'virtual
bool llvm::TargetLowering::isZExtFree(llvm::Type*, llvm::Type*) const'
was hidden [-Werror=overloaded-virtual]
In file included from llvm/lib/Target/ARM/ARMTargetMachine.h:18:0,
from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
llvm/lib/Target/ARM/ARMISelLowering.h:297:18: error: by 'virtual
bool llvm::ARMTargetLowering::isZExtFree(llvm::SDValue, llvm::EVT)
const' [-Werror=overloaded-virtual]
In file included from llvm/lib/Target/ARM/ARMISelLowering.h:23:0,
from llvm/lib/Target/ARM/ARMTargetMachine.h:18,
from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
llvm/include/llvm/Target/TargetLowering.h:1712:16: error: 'virtual
bool llvm::TargetLowering::isZExtFree(llvm::EVT, llvm::EVT) const' was
hidden [-Werror=overloaded-virtual]
In file included from llvm/lib/Target/ARM/ARMTargetMachine.h:18:0,
from llvm/lib/Target/ARM/ARMFastISel.cpp:21:
llvm/lib/Target/ARM/ARMISelLowering.h:297:18: error: by 'virtual
bool llvm::ARMTargetLowering::isZExtFree(llvm::SDValue, llvm::EVT)
const' [-Werror=overloaded-virtual]
> /// isLegalAddressingMode - Return true if the addressing mode represented
> /// by AM is legal for this target, for a load/store of the specified type.
> virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
> @@ -333,11 +335,6 @@
> const SelectionDAG &DAG,
> unsigned Depth) const;
>
> - virtual void computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth) const;
>
> virtual bool ExpandInlineAsm(CallInst *CI) const;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec 6 13:13:27 2012
> @@ -12142,6 +12142,30 @@
> return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
> }
>
> +bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
> + EVT VT1 = Val.getValueType();
> + if (isZExtFree(VT1, VT2))
> + return true;
> +
> + if (Val.getOpcode() != ISD::LOAD)
> + return false;
> +
> + if (!VT1.isSimple() || !VT1.isInteger() ||
> + !VT2.isSimple() || !VT2.isInteger())
> + return false;
> +
> + switch (VT1.getSimpleVT().SimpleTy) {
> + default: break;
> + case MVT::i8:
> + case MVT::i16:
> + case MVT::i32:
> + // X86 has 8, 16, and 32-bit zero-extending loads.
> + return true;
> + }
> +
> + return false;
> +}
> +
> bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
> // i16 instructions are longer (0x66 prefix) and potentially slower.
> return !(VT1 == MVT::i32 && VT2 == MVT::i16);
> @@ -14093,38 +14117,6 @@
> }
> }
>
> -void X86TargetLowering::computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth) const {
> - unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
> - if (Op.getOpcode() == ISD::ANY_EXTEND) {
> - // Implemented as a zero_extend except for i16 -> i32
> - EVT InVT = Op.getOperand(0).getValueType();
> - unsigned InBits = InVT.getScalarType().getSizeInBits();
> - KnownZero = KnownZero.trunc(InBits);
> - KnownOne = KnownOne.trunc(InBits);
> - DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
> - KnownZero = KnownZero.zext(BitWidth);
> - KnownOne = KnownOne.zext(BitWidth);
> - if (BitWidth != 32 || InBits != 16) {
> - APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits);
> - KnownZero |= NewBits;
> - }
> - return;
> - } else if (ISD::isEXTLoad(Op.getNode())) {
> - // Implemented as zextloads or implicitly zero-extended (i32 -> i64)
> - LoadSDNode *LD = cast<LoadSDNode>(Op);
> - EVT VT = LD->getMemoryVT();
> - unsigned MemBits = VT.getScalarType().getSizeInBits();
> - KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
> - return;
> - }
> -
> - assert(0 && "Expecting an ANY_EXTEND or extload!");
> -}
> -
> unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
> unsigned Depth) const {
> // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=169536&r1=169535&r2=169536&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Dec 6 13:13:27 2012
> @@ -558,12 +558,6 @@
> const SelectionDAG &DAG,
> unsigned Depth = 0) const;
>
> - virtual void computeMaskedBitsForAnyExtend(const SDValue Op,
> - APInt &KnownZero,
> - APInt &KnownOne,
> - const SelectionDAG &DAG,
> - unsigned Depth) const;
> -
> // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
> // operation that are sign bits.
> virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
> @@ -634,6 +628,7 @@
> /// result out to 64 bits.
> virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
> virtual bool isZExtFree(EVT VT1, EVT VT2) const;
> + virtual bool isZExtFree(SDValue Val, EVT VT2) const;
>
> /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
> /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
>
>
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