[llvm-commits] [PATCH] Fix typos in FileCheck comments

[Alexander Zinenko]

Thanks, Eli!

Could you or someone else commit it, since I have no commit access?


On 6 December 2012 20:59, Eli Bendersky <eliben at google.com> wrote:

> lgtm
>
> On Thu, Dec 6, 2012 at 10:50 AM, Alexander Zinenko <ftynse at gmail.com>
> wrote:
> > Hello!
> >
> > I caught a typo with misspelled CHECK: comment in a recent clang commit.
> > Having scanned LLVM repository I found out another couple of such typos.
> >
> > Some of them looked intentional, so I fixed only those looking really
> like
> > typos: letters in different order and wrong last symbol.
> >
> > Please, review this patch.
> >
> > --
> > Alexander Zinenko
> >
> > Index: test/Transforms/SROA/vector-promotion.ll
> > ===================================================================
> > --- test/Transforms/SROA/vector-promotion.ll (revision 169521)
> > +++ test/Transforms/SROA/vector-promotion.ll (working copy)
> > @@ -295,7 +295,7 @@
> >  }
> >
> >  define <2 x i8> @PR14349.1(i32 %x) {
> > -; CEHCK: @PR14349.1
> > +; CHECK: @PR14349.1
> >  ; The first testcase for broken SROA rewriting of split integer loads
> and
> >  ; stores due to smaller vector loads and stores. This particular test
> > ensures
> >  ; that we can rewrite a split store of an integer to a store of a
> vector.
> > @@ -317,7 +317,7 @@
> >  }
> >
> >  define i32 @PR14349.2(<2 x i8> %x) {
> > -; CEHCK: @PR14349.2
> > +; CHECK: @PR14349.2
> >  ; The first testcase for broken SROA rewriting of split integer loads
> and
> >  ; stores due to smaller vector loads and stores. This particular test
> > ensures
> >  ; that we can rewrite a split load of an integer to a load of a vector.
> > Index: test/Transforms/InstCombine/mul.ll
> > ===================================================================
> > --- test/Transforms/InstCombine/mul.ll (revision 169521)
> > +++ test/Transforms/InstCombine/mul.ll (working copy)
> > @@ -65,7 +65,7 @@
> >  ; CHECK: @test9
> >          %j = mul i32 %i, -1             ; <i32> [#uses=1]
> >          ret i32 %j
> > -; CHECJ: sub i32 0, %i
> > +; CHECK: sub i32 0, %i
> >  }
> >
> >  define i32 @test10(i32 %a, i32 %b) {
> > Index: test/CodeGen/X86/atom-bypass-slow-division.ll
> > ===================================================================
> > --- test/CodeGen/X86/atom-bypass-slow-division.ll (revision 169521)
> > +++ test/CodeGen/X86/atom-bypass-slow-division.ll (working copy)
> > @@ -35,7 +35,7 @@
> >  ; CHECK: divb
> >  ; CHECK: addl
> >  ; CHECK: ret
> > -; CEECK-NOT: idivl
> > +; CHECK-NOT: idivl
> >  ; CHECK-NOT: divb
> >    %resultdiv = sdiv i32 %a, %b
> >    %resultrem = srem i32 %a, %b
> > @@ -66,7 +66,7 @@
> >
> >  define i32 @test_use_div_reg_imm(i32 %a) nounwind {
> >  ; CHECK: test_use_div_reg_imm
> > -; CEHCK-NOT: test
> > +; CHECK-NOT: test
> >  ; CHECK-NOT: idiv
> >  ; CHECK-NOT: divb
> >    %resultdiv = sdiv i32 %a, 33
> > @@ -75,7 +75,7 @@
> >
> >  define i32 @test_use_rem_reg_imm(i32 %a) nounwind {
> >  ; CHECK: test_use_rem_reg_imm
> > -; CEHCK-NOT: test
> > +; CHECK-NOT: test
> >  ; CHECK-NOT: idiv
> >  ; CHECK-NOT: divb
> >    %resultrem = srem i32 %a, 33
> > @@ -84,7 +84,7 @@
> >
> >  define i32 @test_use_divrem_reg_imm(i32 %a) nounwind {
> >  ; CHECK: test_use_divrem_reg_imm
> > -; CEHCK-NOT: test
> > +; CHECK-NOT: test
> >  ; CHECK-NOT: idiv
> >  ; CHECK-NOT: divb
> >    %resultdiv = sdiv i32 %a, 33
> > Index: test/CodeGen/Thumb2/thumb2-mul.ll
> > ===================================================================
> > --- test/CodeGen/Thumb2/thumb2-mul.ll (revision 169521)
> > +++ test/CodeGen/Thumb2/thumb2-mul.ll (working copy)
> > @@ -15,7 +15,7 @@
> >  ; CHECK: t1:
> >  ; CHECK: mla     r0, r2, r0, r1
> >  ; CHECK: add.w   r0, r0, r0, lsl #3
> > -; CHECL: add.w   r0, r3, r0, lsl #2
> > +; CHECK: add.w   r0, r3, r0, lsl #2
> >    %mul = mul i32 %n, %i
> >    %add = add i32 %mul, %j
> >    %0 = ptrtoint %struct.CMPoint* %thePoints to i32
> > Index: test/CodeGen/ARM/domain-conv-vmovs.ll
> > ===================================================================
> > --- test/CodeGen/ARM/domain-conv-vmovs.ll (revision 169521)
> > +++ test/CodeGen/ARM/domain-conv-vmovs.ll (working copy)
> > @@ -78,7 +78,7 @@
> >    ; use-def chains would be messed up. Primarily a compile-test (we
> used to
> >    ; internal fault).
> >    call void @bar()
> > -; CHECL: bl bar
> > +; CHECK: bl bar
> >  ; CHECK: vext.32
> >  ; CHECK: vext.32
> >    ret float %val
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
>
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