[llvm-commits] [llvm] r166835 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/integer_insertelement.ll test/CodeGen/ARM/vget_lane.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Fri Oct 26 16:39:46 PDT 2012
Author: stoklund
Date: Fri Oct 26 18:39:46 2012
New Revision: 166835
URL: http://llvm.org/viewvc/llvm-project?rev=166835&view=rev
Log:
Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."
Keep the integer_insertelement test case, the new coalescer can handle
this kind of lane insertion without help from pseudo-instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/test/CodeGen/ARM/integer_insertelement.ll
llvm/trunk/test/CodeGen/ARM/vget_lane.ll
Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=166835&r1=166834&r2=166835&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Oct 26 18:39:46 2012
@@ -1208,57 +1208,6 @@
ExpandLaneOp(MBBI);
return true;
- case ARM::VSETLNi8Q:
- case ARM::VSETLNi16Q: {
- // Expand VSETLNs acting on a Q register to equivalent VSETLNs acting
- // on the respective D register.
-
- unsigned QReg = MI.getOperand(1).getReg();
- unsigned QLane = MI.getOperand(3).getImm();
-
- unsigned NewOpcode, DLane, DSubReg;
- switch (Opcode) {
- default: llvm_unreachable("Invalid opcode!");
- case ARM::VSETLNi8Q:
- // 4 possible 8-bit lanes per DPR:
- NewOpcode = ARM::VSETLNi8;
- DLane = QLane % 8;
- DSubReg = (QLane / 8) ? ARM::dsub_1 : ARM::dsub_0;
- break;
- case ARM::VSETLNi16Q:
- // 4 possible 16-bit lanes per DPR.
- NewOpcode = ARM::VSETLNi16;
- DLane = QLane % 4;
- DSubReg = (QLane / 4) ? ARM::dsub_1 : ARM::dsub_0;
- break;
- }
-
- MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpcode));
-
- unsigned DReg = TRI->getSubReg(QReg, DSubReg);
-
- MIB.addReg(DReg, RegState::Define); // Output DPR
- MIB.addReg(DReg); // Input DPR
- MIB.addOperand(MI.getOperand(2)); // Input GPR
- MIB.addImm(DLane); // Lane
-
- // Add the predicate operands.
- MIB.addOperand(MI.getOperand(4));
- MIB.addOperand(MI.getOperand(5));
-
- if (MI.getOperand(1).isKill()) // Add an implicit kill for the Q register.
- MIB->addRegisterKilled(QReg, TRI, true);
- // And an implicit def of the output register (which should always be the
- // same as the input register).
- MIB->addRegisterDefined(QReg, TRI);
-
- TransferImpOps(MI, MIB, MIB);
-
- MI.eraseFromParent();
- return true;
- }
-
case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=166835&r1=166834&r2=166835&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Oct 26 18:39:46 2012
@@ -5140,23 +5140,25 @@
GPR:$R, imm:$lane))]> {
let Inst{21} = lane{0};
}
-
-def VSETLNi8Q : PseudoNeonI<(outs QPR:$V),
- (ins QPR:$src1, GPR:$R, VectorIndex8:$lane),
- IIC_VMOVISL, "",
- [(set QPR:$V, (vector_insert (v16i8 QPR:$src1),
- GPR:$R, imm:$lane))]>;
-def VSETLNi16Q : PseudoNeonI<(outs QPR:$V),
- (ins QPR:$src1, GPR:$R, VectorIndex16:$lane),
- IIC_VMOVISL, "",
- [(set QPR:$V, (vector_insert (v8i16 QPR:$src1),
- GPR:$R, imm:$lane))]>;
}
-
+def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
+ (v16i8 (INSERT_SUBREG QPR:$src1,
+ (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
+ (DSubReg_i8_reg imm:$lane))),
+ GPR:$src2, (SubReg_i8_lane imm:$lane))),
+ (DSubReg_i8_reg imm:$lane)))>;
+def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
+ (v8i16 (INSERT_SUBREG QPR:$src1,
+ (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
+ (DSubReg_i16_reg imm:$lane))),
+ GPR:$src2, (SubReg_i16_lane imm:$lane))),
+ (DSubReg_i16_reg imm:$lane)))>;
def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
- (v4i32 (INSERT_SUBREG QPR:$src1,
- GPR:$src2,
- (SSubReg_f32_reg imm:$lane)))>;
+ (v4i32 (INSERT_SUBREG QPR:$src1,
+ (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
+ (DSubReg_i32_reg imm:$lane))),
+ GPR:$src2, (SubReg_i32_lane imm:$lane))),
+ (DSubReg_i32_reg imm:$lane)))>;
def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
(INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
Modified: llvm/trunk/test/CodeGen/ARM/integer_insertelement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/integer_insertelement.ll?rev=166835&r1=166834&r2=166835&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/integer_insertelement.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/integer_insertelement.ll Fri Oct 26 18:39:46 2012
@@ -6,7 +6,7 @@
; CHECK: @f
; CHECK-NOT: vorr d
-; CHECK: vmov s
+; CHECK: vmov.32 d
; CHECK-NOT: vorr d
; CHECK: mov pc, lr
define <4 x i32> @f(<4 x i32> %in) {
Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=166835&r1=166834&r2=166835&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Fri Oct 26 18:39:46 2012
@@ -200,7 +200,7 @@
define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
;CHECK: vsetQ_lane32:
-;CHECK: vmov s
+;CHECK: vmov.32 d{{.*}}[1], r1
%tmp1 = load <4 x i32>* %A
%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
ret <4 x i32> %tmp2
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