[llvm-commits] [llvm] r165566 - in /llvm/trunk: include/llvm/CodeGen/TargetSchedule.h lib/CodeGen/TargetSchedule.cpp

[Andrew Trick]

Author: atrick
Date: Tue Oct  9 18:44:32 2012
New Revision: 165566

URL: http://llvm.org/viewvc/llvm-project?rev=165566&view=rev
Log:
misched: Add computeInstrLatency to TargetSchedModel.

Modified:
    llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
    llvm/trunk/lib/CodeGen/TargetSchedule.cpp

Modified: llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSchedule.h?rev=165566&r1=165565&r2=165566&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSchedule.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSchedule.h Tue Oct  9 18:44:32 2012
@@ -74,6 +74,14 @@
                                  const MachineInstr *UseMI, unsigned UseOperIdx,
                                  bool FindMin) const;
 
+  /// \brief Compute the instruction latency based on the available machine
+  /// model.
+  ///
+  /// Compute and return the expected latency of this instruction independent of
+  /// a particular use. computeOperandLatency is the prefered API, but this is
+  /// occasionally useful to help estimate instruction cost.
+  unsigned computeInstrLatency(const MachineInstr *MI) const;
+
   /// \brief Identify the processor corresponding to the current subtarget.
   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
 

Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=165566&r1=165565&r2=165566&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Oct  9 18:44:32 2012
@@ -146,6 +146,10 @@
     unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
 
     // Expected latency is the max of the stage latency and itinerary props.
+    // Rather than directly querying InstrItins stage latency, we call a TII
+    // hook to allow subtargets to specialize latency. This hook is only
+    // applicable to the InstrItins model. InstrSchedModel should model all
+    // special cases without TII hooks.
     if (!FindMin)
       InstrLatency = std::max(InstrLatency,
                               TII->defaultDefLatency(&SchedModel, DefMI));
@@ -185,3 +189,23 @@
 #endif
   return 1;
 }
+
+unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
+  if (hasInstrItineraries()) {
+    // For the itinerary model, fall back to the old subtarget hook.
+    return TII->getInstrLatency(&InstrItins, MI);
+  }
+  if (hasInstrSchedModel()) {
+    unsigned Latency = 0;
+    const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
+    for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
+         DefIdx != DefEnd; ++DefIdx) {
+      // Lookup the definition's write latency in SubtargetInfo.
+      const MCWriteLatencyEntry *WLEntry =
+        STI->getWriteLatencyEntry(SCDesc, DefIdx);
+      Latency = std::max(Latency, WLEntry->Cycles);
+    }
+    return Latency;
+  }
+  return TII->defaultDefLatency(&SchedModel, MI);
+}