[llvm-commits] [llvm] r165565 - /llvm/trunk/include/llvm/CodeGen/TargetSchedule.h

[Andrew Trick]

Author: atrick
Date: Tue Oct  9 18:44:29 2012
New Revision: 165565

URL: http://llvm.org/viewvc/llvm-project?rev=165565&view=rev
Log:
misched: Doxument the TargetSchedule API.

Modified:
    llvm/trunk/include/llvm/CodeGen/TargetSchedule.h

Modified: llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSchedule.h?rev=165565&r1=165564&r2=165565&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSchedule.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSchedule.h Tue Oct  9 18:44:29 2012
@@ -37,23 +37,35 @@
 public:
   TargetSchedModel(): STI(0), TII(0) {}
 
+  /// \brief Initialize the machine model for instruction scheduling.
+  ///
+  /// The machine model API keeps a copy of the top-level MCSchedModel table
+  /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
+  /// dynamic properties.
   void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
             const TargetInstrInfo *tii);
 
+  /// \brief TargetInstrInfo getter.
   const TargetInstrInfo *getInstrInfo() const { return TII; }
 
-  /// Return true if this machine model includes an instruction-level scheduling
-  /// model. This is more detailed than the course grain IssueWidth and default
+  /// \brief Return true if this machine model includes an instruction-level
+  /// scheduling model.
+  ///
+  /// This is more detailed than the course grain IssueWidth and default
   /// latency properties, but separate from the per-cycle itinerary data.
   bool hasInstrSchedModel() const;
 
-  /// Return true if this machine model includes cycle-to-cycle itinerary
-  /// data. This models scheduling at each stage in the processor pipeline.
+  /// \brief Return true if this machine model includes cycle-to-cycle itinerary
+  /// data.
+  ///
+  /// This models scheduling at each stage in the processor pipeline.
   bool hasInstrItineraries() const;
 
-  /// computeOperandLatency - Compute and return the latency of the given data
-  /// dependent def and use when the operand indices are already known. UseMI
-  /// may be NULL for an unknown user.
+  /// \brief Compute operand latency based on the available machine model.
+  ///
+  /// Computes and return the latency of the given data dependent def and use
+  /// when the operand indices are already known. UseMI may be NULL for an
+  /// unknown user.
   ///
   /// FindMin may be set to get the minimum vs. expected latency. Minimum
   /// latency is used for scheduling groups, while expected latency is for
@@ -62,7 +74,10 @@
                                  const MachineInstr *UseMI, unsigned UseOperIdx,
                                  bool FindMin) const;
 
+  /// \brief Identify the processor corresponding to the current subtarget.
   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
+
+  /// \brief Maximum number of micro-ops that may be scheduled per cycle.
   unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
 
 private: