[llvm-commits] [PATCH] Prevent the mixing of S and D registers for vsqrt/vdiv instructions on A15

[Silviu Baranga]

It turns out that the PseudoInst can be expanded using only
TableGen definitions. I've updated the patch and attached it.

-- Silviu

> -----Original Message-----
> From: Silviu Baranga [mailto:silbar01 at arm.com]
> Sent: 28 September 2012 13:57
> To: 'Tim Northover'; Jim Grosbach
> Cc: llvm-commits at cs.uiuc.edu
> Subject: RE: [llvm-commits] [PATCH] Prevent the mixing of S and D
> registers for vsqrt/vdiv instructions on A15
> 
> Hi Jim,
> 
> I've used Tim's suggestion and replaced the CodeGenOnly
> definition with a PseudoInst.
> 
> The new patch is attached.
> 
> Thanks,
> Silviu
> 
> > -----Original Message-----
> > From: Tim Northover [mailto:t.p.northover at gmail.com]
> > Sent: 28 September 2012 07:19
> > To: Jim Grosbach
> > Cc: Silviu Baranga; llvm-commits at cs.uiuc.edu
> > Subject: Re: [llvm-commits] [PATCH] Prevent the mixing of S and D
> > registers for vsqrt/vdiv instructions on A15
> >
> > Hi Jim,
> >
> > > The duplicated instruction is a non-starter. We're working hard to
> > > get rid of CodeGenOnly definitions. The pattern should be
> > > representable in another way using the existing instruction
> > > definition.
> > >
> > > That is, the instruction definitions represent exactly that, the
> > > instructions. That's completely orthogonal to using NEON for scalar
> > > floating point.
> >
> > Hmm. At a tangent, I can see how CodeGenOnly can be replaced (a
> normal
> > PseudoInst expanded PostRA), but does this strictness apply to
> > isAsmParserOnly too? I don't think InstAlias is up to the job of
> > replacing it yet, at least while maintaining a sane operand
> > arrangement.
> >
> > Tim.
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