[llvm-commits] [PATCH] Prevent the mixing of S and D registers for vsqrt/vdiv instructions on A15

[Silviu Baranga]

Hi Jim,

I've used Tim's suggestion and replaced the CodeGenOnly
definition with a PseudoInst.

The new patch is attached.

Thanks,
Silviu

> -----Original Message-----
> From: Tim Northover [mailto:t.p.northover at gmail.com]
> Sent: 28 September 2012 07:19
> To: Jim Grosbach
> Cc: Silviu Baranga; llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Prevent the mixing of S and D
> registers for vsqrt/vdiv instructions on A15
> 
> Hi Jim,
> 
> > The duplicated instruction is a non-starter. We're working hard to
> > get rid of CodeGenOnly definitions. The pattern should be
> > representable in another way using the existing instruction
> > definition.
> >
> > That is, the instruction definitions represent exactly that, the
> > instructions. That's completely orthogonal to using NEON for scalar
> > floating point.
> 
> Hmm. At a tangent, I can see how CodeGenOnly can be replaced (a normal
> PseudoInst expanded PostRA), but does this strictness apply to
> isAsmParserOnly too? I don't think InstAlias is up to the job of
> replacing it yet, at least while maintaining a sane operand
> arrangement.
> 
> Tim.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: sqrt_div_neonfp_a15.diff
Type: application/octet-stream
Size: 4579 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20120928/660e99d5/attachment.obj>