[llvm-commits] [llvm] r159162 - /llvm/trunk/include/llvm/Target/Target.td

[Owen Anderson]

On Jun 25, 2012, at 2:33 PM, Tom Stellard <thomas.stellard at amd.com> wrote:

> Do you have a simple tablegen example that uses this new class? It seems
> useful, but I don't quite understand how it is supposed to be used.

Suppose you have an ISA where many operands can be either a (one of many kinds of) register or an immediate.  Right now we have code like this today in ARM NEON, for example:

multi class MyAwesomeInstruction<RegisterClass dst_class, RegisterClass src0_class, RegisterClass src1_class> {
  def foo : Inst<(outs dst_class:$dst), (ins src0_class:$src0, src1_class:$src1), … >;
  ...
}

def FOOr8r8r8 : MyAwesomeInstruction<GPR8, GPR8, GPR8>;
def FOOr32r8r8 : MyAwesomeInstruction<GPR32, GPR8, GPR8>;
…

By using DAGOperand, you can now write multi classes that are polymorphic over Operand's as well as RegisterClass's, allowing this:

multi class MyAwesomeInstruction<RegisterClass dst_class, DAGOperand src0_class, DAGOperand src1_class> {
  def foo : Inst<(outs dst_class:$dst), (ins src0_class:$src0, src1_class:$src1), … >;
  ...
}

def MyAwesomeImmediateFormat : Operand<i32>;

def FOOr8r8r8 : MyAwesomeInstruction<GPR8, GPR8, GPR8>;
def FOOr32r8r8 : MyAwesomeInstruction<GPR32, GPR8, GPR8>;
def FOOr32r8i32 : MyAwesomeInstruction<GPR32, GPR8, MyAwesomeImmediateFormat>;
…

--Owen