[llvm-commits] [PATCH] Missing bit definition for STR post reg instruction on ARM

[Silviu Baranga]

Hi,

 

The 4th bit of the STR (post reg) instruction in the ARM backend is
currently not defined. It should be set

to 0. This is causing other instructions(such as SEL) to be disassembled as
STR instructions. The patch

adds the missing definition. 

 

The instructions that were being wrongly disassembled as STR instructions
also had missing unpredictable  

bitfield specifications. The patch also sets the bits in the "Unpredictable"
mask for these instructions.

 

We add regression tests for all the affected instructions.

 

Please review this patch.

 

Thanks,

Silviu
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