[llvm-commits] [llvm] r156539 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-vbroadcast.ll
Nadav Rotem
nadav.rotem at intel.com
Thu May 10 05:22:05 PDT 2012
Author: nadav
Date: Thu May 10 07:22:05 2012
New Revision: 156539
URL: http://llvm.org/viewvc/llvm-project?rev=156539&view=rev
Log:
Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program.
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.
Fix PR11900.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=156539&r1=156538&r2=156539&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu May 10 07:22:05 2012
@@ -5029,10 +5029,6 @@
if (!ISD::isNormalLoad(Ld.getNode()))
return SDValue();
- // Reject loads that have uses of the chain result
- if (Ld->hasAnyUseOfValue(1))
- return SDValue();
-
unsigned ScalarSize = Ld.getValueType().getSizeInBits();
if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
Modified: llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll?rev=156539&r1=156538&r2=156539&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll Thu May 10 07:22:05 2012
@@ -112,3 +112,20 @@
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
ret <2 x double> %vecinit2.i
}
+
+; CHECK: _RR
+; CHECK: vbroadcastss (%
+; CHECK: ret
+define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
+entry:
+ %q = load float* %ptr, align 4
+ %vecinit.i = insertelement <4 x float> undef, float %q, i32 0
+ %vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
+ %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
+ %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
+ ; force a chain
+ %j = load i32* %k, align 4
+ store i32 %j, i32* undef
+ ret <4 x float> %vecinit6.i
+}
+
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