[llvm-commits] [PATCH 06/11] (patch) Mips specific inline asm: constraint 'L':

[Jack Carter]

A signed 32 bit  constant in which the lower 16 bits are zero.

Example:
  // Good: i_val fits the criteria
  int i_input = 0x00000400; int i_result = 0; int i_tmp = 0;

  int i_val = 0x00100000;
  __asm__ __volatile__(
    "add %0,%1,%3\n\t" : "=r" (i_result) : "r" (i_input), "L" (i_val), "r" (i_tmp));

  // Bad: llc should complain
  int i_val = 0x00100003;
  __asm__ __volatile__(
    "add %0,%1,%3\n\t" : "=r" (i_result)  : "r" (i_input), "L" (i_val), "r" (i_tmp));
---
 lib/Target/Mips/MipsISelLowering.cpp         |   11 +++++++++++
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll |   13 +++++++++++++
 test/CodeGen/Mips/inlineasm_constraint.ll    |    7 ++++++-
 3 files changed, 30 insertions(+), 1 deletions(-)
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll

-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index c1d6a88..a2c69b7 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2929,6 +2929,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
   case 'I': // signed 16 bit immediate
   case 'J': // integer zero
   case 'K': // unsigned 16 bit immediate
+  case 'L': // signed 32 bit immediate where lower 16 bits are 0
     if (isa<ConstantInt>(CallOperandVal))
       weight = CW_Constant;
     break;
@@ -3012,6 +3013,16 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
       }
     }
     return;
+  case 'L': // signed 32 bit immediate where lower 16 bits are 0
+    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+      EVT Type = Op.getValueType();
+      int64_t Val = C->getSExtValue();
+      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
+        Result = DAG.getTargetConstant(Val, Type);
+        break;
+      }
+    }
+    return;
   }
 
   if (Result.getNode()) {
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
new file mode 100644
index 0000000..e23ab6f
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
@@ -0,0 +1,13 @@
+;XFAIL:
+;
+;This is a negative test. The constant value given for the constraint (L)
+;is non-zero in the lower 16 bits (0x00100003).
+;
+; RUN: not llc -march=mipsel < %s 
+
+define i32 @main() nounwind {
+entry:
+  tail call i32 asm "addi $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind
+  ret i32 0
+}
+
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll
index 04bd513..34d0657 100644
--- a/test/CodeGen/Mips/inlineasm_constraint.ll
+++ b/test/CodeGen/Mips/inlineasm_constraint.ll
@@ -27,6 +27,11 @@ entry:
 ; CHECK: #NO_APP	
   tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
 
+; Now L with 0x00100000
+; CHECK: #APP
+; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}}
+; CHECK: #NO_APP	
+  tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
+
   ret i32 0
 }
-