[llvm-commits] [PATCH 4/4] (REVIEW REQUEST) Mips specific constraint 'K':

[Jack Carter]

An unsigned 16 bit constant.

Example:
  int i_input = 0x00000400; int i_result = 0; int i_tmp = 0;

  // Good: i_val fits the criteria
  int i_val = 64;
  __asm__ __volatile__(
    "add %0,%1,%3\n\t" : "=r" (i_result) : "r" (i_input), "K" (i_val), "r" (i_tmp));

  // Bad: llc should complain
  int i_val = 0x00100003;
  __asm__ __volatile__(
    "add %0,%1,%3\n\t" : "=r" (i_result)  : "r" (i_input), "K" (i_val), "r" (i_tmp));
---
 lib/Target/Mips/MipsISelLowering.cpp         |   14 ++++++++++++++
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll |   16 ++++++++++++++++
 test/CodeGen/Mips/inlineasm_constraint.ll    |   10 +++++++++-
 3 files changed, 39 insertions(+), 1 deletions(-)
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 9240831..129415e 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2928,6 +2928,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
     break;
   case 'I': // signed 16 bit immediate
   case 'J': // integer zero
+  case 'K': // unsigned 16 bit immediate
     if (isa<ConstantInt>(CallOperandVal))
       weight = CW_Constant;
     break;
@@ -3010,6 +3011,19 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
       }
     }
     return;
+  case 'K': // unsigned 16 bit immediate
+    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+      // GCC allows both shorts and ints
+      if (!((Op.getValueType() == MVT::i16) || (Op.getValueType() == MVT::i32)))
+        return; // This will produce an error
+
+      uint32_t Val = (uint32_t)C->getZExtValue();
+      if ((Val & 0xffff0000) == 0) {
+        Result = DAG.getTargetConstant(Val, Op.getValueType());
+        break;
+      }
+    }
+    return;
   }
 
   if (Result.getNode()) {
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
new file mode 100644
index 0000000..05abfe8
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
@@ -0,0 +1,16 @@
+;XFAIL:
+;
+;This is a negative test. The constant value given for the constraint (K)
+;is greater than 16 bits (0x00100000).
+;
+; RUN: not llc -march=mipsel < %s 
+
+ at .str = private unnamed_addr constant [23 x i8] c"mips_addi(%d,%d) = %d\0A\00", align 1
+
+define i32 @main() nounwind {
+entry:
+  %0 = tail call i32 asm "addu $0,$1,$2", "=r,r,K"(i32 1024, i32 1048576) nounwind, !srcloc !0
+  ret i32 0
+}
+
+!0 = metadata !{i32 148}
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll
index 4752411..cb91a7b 100644
--- a/test/CodeGen/Mips/inlineasm_constraint.ll
+++ b/test/CodeGen/Mips/inlineasm_constraint.ll
@@ -17,12 +17,20 @@ entry:
 
 ; Now J with 0
 ; CHECK: #APP
-; CHECK: addi $2,$2,0
+; CHECK: addi $3,$2,0
 ; CHECK: #NO_APP
   %2 = tail call i32 asm sideeffect "addi $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind, !srcloc !2
+
+; Now K with 64
+; CHECK: #APP
+; CHECK: addu $2,$2,64
+; CHECK: #NO_APP	
+  %3 = tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind, !srcloc !2
+
   ret i32 0
 }
 
 !0 = metadata !{i32 133, i32 149}
 !1 = metadata !{i32 466}
 !2 = metadata !{i32 537, i32 553}
+!3 = metadata !{i32 795, i32 811}